Bharani Thiruvengadam
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2001–2001
Best venue rank
B
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2001 | FPL | Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. | Andreas Dandalis, Viktor K. Prasanna, Bharani Thiruvengadam |