Bheema Rao Nistala
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2023–2023
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | VLSID | A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET. | Thota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala |