A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET.
Thota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala
Browse the full VLSID paper archive.
Thota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala
Browse the full VLSID paper archive.