Siva Kumar Rapina
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2023–2025
Best venue rank
National
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | VLSID | 8GHz Multi-Phase Ring VCO Design with Wide Tuning Range for SerDes Applications in 6nm FinFET Process. | Ravuru Vasudeva Reddy, Siva Kumar Rapina, Siddhartha Hazra, K. Sarangam |
| 2024 | VLSID | Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications. | Marichamy Divya, Siva Kumar Rapina, S. Kumaravel |
| 2023 | VLSID | A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET. | Thota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala |