Bo-Yi Chiang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2006–2007
Best venue rank
National
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2007 | VLSID | Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization. | Jin-Tai Yan, Bo-Yi Chiang |
| 2006 | ISCAS | Timing-constrained yield-driven wire sizing for critical area minimization. | Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee |