Chandrajit Debnath
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2010–2010
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | VLSID | A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process. | Arunkumar Salimath, Chandrajit Debnath, Kallol Chatterjee, Sushanta K. Mandal |