Chao-Yang Yeh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2003–2005
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | FPGA | Skew-programmable clock design for FPGA and skew-aware placement. | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
| 2005 | ICCAD | A sliding window scheme for accurate clock mesh analysis. | Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai |
| 2005 | ICCAD | Timing-aware power noise reduction in layout. | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
| 2003 | DAC | Delay budgeting in sequential circuit with application on FPGA placement. | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
| 2003 | ICCAD | Minimum-Area Sequential Budgeting for FPGA. | Chao-Yang Yeh, Malgorzata Marek-Sadowska |