| 2019 | DATE | Package and Chip Accelerated Aging Methods for Power MOSFET Reliability Evaluation. | Ting-You Lin, Chauchin Su, Chung-Chih Hung, Karuna Nidhi, Chily Tu, Shao-Chang Huang |
| 2010 | ISCAS | A 5Gb/s pulse signaling interface for low power on-chip data communication. | Hung-Wen Lin, Yingchieh Ho, YingLin Fa, Chauchin Su |
| 2006 | ASPDAC | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. | Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen |
| 2006 | SMC | Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H∞ Filter. | Chih-Hu Wang, Bore-Kuen Lee, Wei-Hang Tseng, Chung-Hsi Fu, Chauchin Su, Chien-Nan Jimmy Liu |
| 2005 | ASPDAC | Oscillation ring based interconnect test scheme for SOC. | Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen |
| 2005 | ISCAS | A spread spectrum clock generator for SATA-II. | Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su |
| 2003 | ASPDAC | A novel LCD driver testing technique using logic test channels. | Chauchin Su, Wei-Juo Wang, Chih-Hu Wang, I. S. Tseng |
| 2003 | VTS | 1149.4 Based On-Line Quiescent State Monitoring Technique. | Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, I. S. Tseng |
| 2001 | ASPDAC | A computer aided engineering system for memory BIST. | Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee |
| 2001 | ITC | Configuration free SoC interconnect BIST methodology. | Chauchin Su, Wenliang Tseng |
| 2001 | VTS | Test Waveform Shaping in Mixed Signal Test Bus by Pre-Equalization. | Yue-Tsang Chen, Chauchin Su |
| 2000 | DATE | All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. | Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee |
| 2000 | VTS | Crosstalk Effect Removal for Analog Measurement in Analog Test Bus. | Chauchin Su, Yue-Tsang Chen |
| 1998 | ICCAD | A linear optimal test generation algorithm for interconnect testing. | Chauchin Su |
| 1998 | ITC | Boundary scan BIST methodology for reconfigurable systems. | Chauchin Su, Shung-Won Jeng, Yue-Tsang Chen |
| 1997 | ASPDAC | Structural approach for performance driven ECC circuit synthesis. | Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou |
| 1997 | ITC | Parasitic Effect Removal for Analog Measurement in P1149.4 Environment. | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou |
| 1996 | DATE | Decentralized BIST for 1149.1 and 1149.5 Based Interconnects. | Chauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting |
| 1996 | ICCAD | Metrology for analog module testing using analog testability bus. | Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tzu Ting |
| 1995 | ICCAD | Impulse response fault model and fault extraction for functional level analog circuit diagnosis. | Chauchin Su, Shenshung Chiang, Shyh-Jye Jou |
| 1995 | ISCAS | A Parallel Event-Driven MOS Timing Simulator on Distributed-Memory Multiprocessors. | Wen-Hsing Hsieh, Shyh-Jye Jou, Chauchin Su |
| 1995 | ISCAS | Circuits Design Optimization Using Symbolic Approach. | Shyh-Jye Jou, Kou-Fong Liu, Chauchin Su |
| 1994 | ISCAS | Hierarchical Techniques for Symbolic Analysis of Large Electronic Circuits. | Shyh-Jye Jou, Mei-Fang Perng, Chauchin Su, C. K. Wang |
| 1994 | ITC | An I | Chauchin Su, Kychin Hwang, Shyh-Jye Jou |
| 1993 | ISCAS | A Universal BIST Methodology for Interconnects. | Chiyuan Chang, Chauchin Su |
| 1993 | ISCAS | ECCSyn: a Synthesis Tool for ECC Circuits. | Chauchin Su, Jyrghong Wang |
| 1993 | ITC | A Serial-Scan Test-Vector-Compression Methodology. | Chauchin Su, Kychin Hwang |