Chethan Kumar H. B
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2017–2017
Best venue rank
A
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | FPGA | 120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board. | Chethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre |