Chi-Feng Wu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
6
Active years
1999–2014
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | DATE | Mask-cost-aware ECO routing | Hsi-An Chien, Zhen-Yu Peng, Yun-Ru Wu, Ting-Hsiung Wang, Hsin-Chang Lin, Chi-Feng Wu, Ting-Chi Wang |
| 2009 | ITC | A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. | Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu |
| 2001 | DAC | Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories. | Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Chih-Wea Wang, Cheng-Wen Wu |
| 2000 | ICCAD | Error Catch and Analysis for Semiconductor Memories Using March Tests. | Chi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu |
| 2000 | VTS | Simulation-Based Test Algorithm Generation for Random Access Memories. | Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu |
| 1999 | ASPDAC | Testing Interconnects of Dynamic Reconfigurable FPGAs. | Chi-Feng Wu, Cheng-Wen Wu |