| 2025 | ASPDAC | In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis. | You-Kai Zheng, Ming-Liang Wei, Hsiang-Yun Cheng, Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong, Po-Hao Tseng, Hsiang-Pang Li |
| 2025 | DATE | Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices. | Jing-Jia Hung, Yi-Jung Chen, Hsiang-Yun Cheng, Hsu Kao, Chia-Lin Yang |
| 2025 | DATE | REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Learning-Based Attacks. | Hassan Nassar, Ming-Liang Wei, Chia-Lin Yang, Jrg Henkel, Kuan-Hsun Chen |
| 2025 | ICCAD | Accelerating Genome Alignment Pipeline with In-NAND Search Technology and Group Testing Techniques. | Ming-Hsiang Tsai, Ming-Liang Wei, Chia-Chun Chien, Po-Hao Tseng, Yung-Chun Lee, Hsiang-Pang Li, Chia-Lin Yang |
| 2024 | ICCAD | Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications. | Jrg Henkel, Lokesh Siddhu, Hassan Nassar, Lars Bauer, Jian-Jia Chen, Christian Hakert, Tristan Taylan Seidl, Kuan-Hsun Chen, Xiaobo Sharon Hu, Mengyuan Li, Chia-Lin Yang, Ming-Liang Wei |
| 2024 | MICRO | PointCIM: A Computing-in-Memory Architecture for Accelerating Deep Point Cloud Analytics. | Xuan-Jun Chen, Han-Ping Chen, Chia-Lin Yang |
| 2024 | SYSTOR | RecTS: A Temporal-Aware Memory System Optimization for Training Deep Learning Recommendation Models. | Cheng-Yu Chen, Jui-Nan Yen, You-Ru Lai, Yun-Ping Lin, Chia-Lin Yang |
| 2023 | CASES | Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. | Jrg Henkel, Lokesh Siddhu, Lars Bauer, Jrgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jernimo Castrilln, Asif Ali Khan, Hamid Farzaneh, Joo Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng |
| 2023 | DAC | Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators by Layerwise Dynamical Isometry. | Xuan-Jun Chen, Cynthia Kuan, Chia-Lin Yang |
| 2023 | HPCA | Tensor Movement Orchestration in Multi-GPU Training Systems. | Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang |
| 2023 | VTS | Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories. | Mikail Yayla, Simon Thomann, Md. Mazharul Islam, Ming-Liang Wei, Shu-Yin Ho, Ahmedullah Aziz, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch |
| 2022 | ASPDAC | PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. | Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang |
| 2022 | ASPDAC | This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. | Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai |
| 2022 | HPCA | RM-SSD: In-Storage Computing for Large-Scale Recommendation Inference. | Xuan Sun, Hu Wan, Qiao Li, Chia-Lin Yang, Tei-Wei Kuo, Chun Jason Xue |
| 2022 | HPCA | Efficient Bad Block Management with Cluster Similarity. | Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo |
| 2021 | DATE | Future Computing Platform Design: A Cross-Layer Design Approach. | Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo |
| 2021 | ICCAD | Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through Binarization. | Ming-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Chia-Lin Yang, Hussam Amrouch |
| 2021 | ISCAS | A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads. | Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien |
| 2021 | ISPASS | Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. | Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang |
| 2020 | DAC | Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. | Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li |
| 2019 | ICCAD | The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. | Jrg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang |
| 2019 | ICIP | Iotbench: A Benchmark Suite for Intelligent Internet of Things Edge Devices. | Chien-I Lee, Meng-Yao Lin, Chia-Lin Yang, Yen-Kuang Chen |
| 2019 | ISCA | Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. | Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li |
| 2018 | DAC | Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. | Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang |
| 2018 | ICCAD | DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. | Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang |
| 2017 | ASPDAC | Enabling fast preemption via Dual-Kernel support on GPUs. | Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang |
| 2017 | DAC | Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach. | Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang |
| 2017 | ISLPED | Message from the general co-chairs. | David Garrett, Chia-Lin Yang |
| 2017 | ISPASS | Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. | Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung |
| 2016 | ASPDAC | MCSSim: A memory channel storage simulator. | Renhai Chen, Zili Shao, Chia-Lin Yang, Tao Li |
| 2016 | DAC | Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. | Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang |
| 2015 | ISLPED | Fine-grained write scheduling for PCM performance improvement under write power budget. | Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li |
| 2015 | MICRO | Improving DRAM latency with dynamic asymmetric subarray. | Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang |
| 2014 | ASPLOS | NVM duet: unified working memory and persistent store architecture. | Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Shun-Chih Yu, Cheng-Yuan Michael Wang |
| 2014 | DAC | EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. | Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li |
| 2013 | DAC | DuraCache: a durable SSD cache using MLC NAND flash. | Ren-Shuo Liu, Chia-Lin Yang, Cheng-Hsuan Li, Geng-You Chen |
| 2013 | ISLPED | Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. | Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu |
| 2012 | ASPDAC | Memory access aware power gating for MPSoCs. | Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang |
| 2012 | DAC | Age-based PCM wear leveling with nearly zero search cost. | Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, Cheng-Yuan Michael Wang |
| 2012 | FAST | Optimizing NAND flash-based SSDs via retention relaxation. | Ren-Shuo Liu, Chia-Lin Yang, Wei Wu |
| 2012 | ICCAD | Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. | Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen |
| 2012 | ICCD | SECRET: Selective error correction for refresh energy reduction in DRAMs. | Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang |
| 2012 | ISPASS | A cycle-level SIMT-GPU simulation framework. | Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng |
| 2010 | DATE | PM-COSYN: PE and memory co-synthesis for MPSoCs. | Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang |
| 2010 | ICCAD | Hierarchical memory scheduling for multimedia MPSoCs. | Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang |
| 2010 | ISLPED | Dynamic thermal management for networked embedded systems under harsh ambient temperature variation. | Sangyoung Park, Jian-Jia Chen, Donghwa Shin, Younghyun Kim, Chia-Lin Yang, Naehyuck Chang |
| 2010 | MICRO | Memory Latency Reduction via Thread Throttling. | Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang |
| 2009 | ICCAD | Thermal modeling for 3D-ICs with integrated microchannel cooling. | Hitoshi Mizunuma, Chia-Lin Yang, Yi-Chang Lu |
| 2009 | ISLPED | PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. | Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King |
| 2008 | DAC | A progressive-ILP based routing algorithm for cross-referencing biochips. | Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang |
| 2007 | CASES | Cache leakage control mechanism for hard real-time systems. | Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen |
| 2007 | DATE | Energy-efficient real-time task scheduling with task rejection. | Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei King |
| 2007 | ICCAD | BioRoute: a network-flow based routing algorithm for digital microfluidic biochips. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2007 | ISLPED | Post-placement leakage optimization for partially dynamically reconfigurable FPGAs. | Chi-Feng Li, Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2007 | SAC | An architectural co-synthesis algorithm for energy-aware network-on-chip design. | Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su |
| 2006 | DAC | Placement of digital microfluidic biochips using the t-tree formulation. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2006 | ISLPED | Hierarchical value cache encoding for off-chip data bus. | Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King |
| 2006 | ISLPED | An energy-efficient virtual memory system with flash memory as the secondary storage. | Hung-Wei Tseng, Han-Lin Li, Chia-Lin Yang |
| 2006 | ISORC | A Space-Efficient Caching Mechanism for Flash-Memory Address Translation. | Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang |
| 2005 | ISLPED | Joint exploration of architectural and physical design spaces with thermal consideration. | Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang |
| 2005 | RTCSA | Reconfigurable Platform for Content Science Research. | Chi-Sheng Shih, Chia-Lin Yang, Mong-Kai Ku, Tei-Wei Kuo, Shao-Yi Chien, Yao-Wen Chang, Liang-Gee Chen |
| 2004 | ASPDAC | Temporal floorplanning using 3D-subTCG. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen |
| 2004 | DATE | Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. | Yen-Jen Chang, Chia-Lin Yang, Feipei Lai |
| 2004 | ECRTS | Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations. | Jian-Jia Chen, Heng-Ruey Hsu, Kai-Hsiang Chuang, Chia-Lin Yang, Ai-Chun Pang, Tei-Wei Kuo |
| 2004 | ICCAD | Temporal floorplanning using the T-tree formulation. | Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang |
| 2004 | ISLPED | HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction. | Chia-Lin Yang, Chien-Hao Lee |
| 2004 | SAC | Profit-driven uniprocessor scheduling with energy and timing constraints. | Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang |
| 2003 | ISLPED | A power-aware SWDR cell for reducing cache write power. | Yen-Jen Chang, Chia-Lin Yang, Feipei Lai |
| 2000 | ICS | Push vs. pull: data movement for linked data structures. | Chia-Lin Yang, Alvin R. Lebeck |
| 1999 | EuroPar | Annotated Memory References: A Mechanism for Informed Cache Management. | Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi |
| 1998 | MICRO | Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. | Chia-Lin Yang, Barton Sano, Alvin R. Lebeck |