Chia-Pin R. Liu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
2
Active years
2006–2009
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | CAINE | Floorplan Optimization for Hierarchical VLSI Design. | Chia-Pin R. Liu |
| 2009 | CATA | A Novel Floorplanning for Hierarchical VLSI Design. | Chia-Pin R. Liu |
| 2008 | CAINE | A Novel Synthesis for Dynamic CMOS Circuits. | Chia-Pin R. Liu |
| 2007 | CAINE | Gate Model Extraction from CMOS Transistor Circuits. | Chia-Pin R. Liu |
| 2006 | CAINE | Transistor-mapped binary decision diagram for CMOS circuits. | Chia-Pin R. Liu |
| 2006 | CATA | Traffic Monitoring for a Network Visualization Environment. | Chia-Pin R. Liu, Shaofeng Yang, Mahmound A. Manzoul |