Chin Hau Hoo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
4
Active years
2012–2018
Best venue rank
B
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | FPGA | ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling. | Chin Hau Hoo, Akash Kumar |
| 2017 | FCCM | ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding. | Chin Hau Hoo, Akash Kumar |
| 2016 | FPL | ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. | Chin Hau Hoo, Yajun Ha, Akash Kumar |
| 2015 | FPL | ParaLaR: A parallel FPGA router based on Lagrangian relaxation. | Chin Hau Hoo, Akash Kumar, Yajun Ha |
| 2013 | FPL | A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm. | Chin Hau Hoo, Yajun Ha, Akash Kumar |
| 2013 | ISLPED | Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. | Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez |
| 2012 | FPL | An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay. | Chin Hau Hoo, Akash Kumar |