| 2015 | ISCAS | Memory-efficient discrete wavelet transform architecture based on wordlength optimization. | Yusong Hu, Ching-Chuen Jong |
| 2013 | ISCAS | Non-iterative high speed division computation based on Mitchell logarithmic method. | Joshua Yung Lih Low, Ching-Chuen Jong |
| 2012 | ISCAS | A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. | Joshua Yung Lih Low, Ching-Chuen Jong, Jeremy Yung Shern Low, Thian Fatt Tay, Chip-Hong Chang |
| 2010 | ISCAS | A novel counter-based low complexity inner-product architecture for high speed inputs. | Manas Ranjan Meher, Ching-Chuen Jong, Chip-Hong Chang, Jeremy Yung Shern Low |
| 2009 | ISCAS | Time-multiplexed Data Flow Graph for the Design of Configurable Multiplier Block. | Jiajia Chen, Chip-Hong Chang, Ching-Chuen Jong |
| 2006 | ISCAS | A new integrated approach to the design of low-complexity FIR filters. | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong |
| 2005 | ISCAS | Using symbolic computer algebra for subexpression factorization and subexpression decomposition in high level synthesis. | Xianwu Xing, Ching-Chuen Jong |
| 2005 | ISCAS | I | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong |
| 2004 | ICASSP | Efficient algorithms for common subexpression elimination in digital filter design. | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong |
| 2004 | ISCAS | HWP: a new insight into canonical signed digit. | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong |
| 2004 | ISCAS | A new contention resolution algorithm for the design of minimal logic depth multiplierless filters. | Fei Xu, Chip-Hong Chang, Ching-Chuen Jong |
| 1999 | ISCAS | A lower bound on general minimal resource interval scheduling with arbitrary component selection. | Z. X. Shen, Ching-Chuen Jong |
| 1997 | FPL | FPGA implementation of a digital IQ demodulator using VHDL. | Ching-Chuen Jong, Y. Y. H. Lam, L. S. Ng |
| 1994 | ISCAS | Time-Zone: A New Algorithm for Register Allocation in Data Path Synthesis. | Ching-Chuen Jong, Y. Y. H. Lam, S. S. Lim, T. S. Teng |