Ching-Nen Peng
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
2012–2016
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | DAC | Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. | Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
| 2014 | ITC | Wafer Level Chip Scale Package copper pillar probing. | Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
| 2014 | ITC | Redundancy architectures for channel-based 3D DRAM yield improvement. | Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
| 2014 | VTS | A 4-GHz universal high-frequency on-chip testing platform for IP validation. | Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang |
| 2013 | ITC | Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch. | Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang |
| 2012 | ITC | A memory yield improvement scheme combining built-in self-repair and error correction codes. | Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang |