Chingwei Yeh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
4
Active years
1999–2022
Best venue rank
A*
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | ASPDAC | A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. | Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang |
| 2006 | DAC | Timing driven power gating. | De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh |
| 2006 | DATE | An 830mW, 586kbps 1024-bit RSA chip design. | Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang |
| 2006 | DATE | A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. | Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang |
| 2006 | ISCAS | Design of STR level converters for SoCs using the multi-island dual-VDD design technique. | Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu |
| 2005 | ASPDAC | Power minimization for dynamic PLAs. | Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh |
| 2005 | ISCAS | A low-power high-SFDR CMOS direct digital frequency synthesizer. | Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh |
| 1999 | ISCAS | Power reduction through iterative gate sizing and voltage scaling. | Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone |
| 1999 | ISCAS | A cell selection strategy for low power applications. | Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang |
| 1999 | ISCAS | A simulated annealing based method supporting dual supply voltages in standard cell placement. | Chingwei Yeh, Yin-Shuin Kang |