| 2022 | ISCAS | Hardware Implementation of High-Performance Polynomial Multiplication for KEM Saber. | Yazheng Tu, Pengzhou He, Chiou-Yng Lee, Danai Chasaki, Jiafeng Xie |
| 2021 | ICCD | CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy. | Jiafeng Xie, Pengzhou He, Chiou-Yng Lee |
| 2020 | ASPDAC | Efficient Subquadratic Space Complexity Digit-Serial Multipliers over GF(2 | Chiou-Yng Lee, Jiafeng Xie |
| 2019 | FPGA | Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity. | Jiafeng Xie, Chiou-Yng Lee |
| 2019 | ICCD | Efficient Scalable Three Operand Multiplier Over GF(2^m) Based on Novel Decomposition Strategy. | Chiou-Yng Lee, Jiafeng Xie |
| 2019 | ISCAS | Low-Complexity Systolic Multiplier for GF(2 | Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher |
| 2018 | ICCD | Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm. | Chiou-Yng Lee, Jiafeng Xie |
| 2015 | ISCAS | Efficient subquadratic parallel multiplier based on modified SPB of GF(2 | Jeng-Shyang Pan, Pramod Kumar Meher, Chiou-Yng Lee, Hong-Hai Bai |
| 2010 | AINA | Concurrent Error Detection in Shifted Dual Basis Multiplier over GF(2m) Using Cyclic Code Approach. | Chiou-Yng Lee, Yu-Hsin Chiu, Jung-Hui Chiu |
| 2010 | ISPA | Error-Correcting Codes for Concurrent Error Correction in Bit-Parallel Systolic and Scalable Multipliers for Shifted Dual Basis of GF(2 | Chiou-Yng Lee |
| 2009 | ASPDAC | An optimized design for serial-parallel finite field multiplication over | Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee |
| 2009 | ISCAS | Scalable Serial-parallel Multiplier over GF(2 | Pramod Kumar Meher, Chiou-Yng Lee |
| 2008 | AINA | Concurrent Error Detection in Digit-Serial Normal Basis Multiplication over GF(2m). | Chiou-Yng Lee |
| 2008 | APSCC | Efficient Bit-Parallel Multipliers in Composite Fields. | Chiou-Yng Lee, Pramod Kumar Meher |
| 2007 | AINA | Low-Complexity Parallel Systolic Architectures for Computing Multiplication and Squaring over FG(2 | Chiou-Yng Lee, Yung-Hui Chen |
| 2006 | SMC | Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m). | Chiou-Yng Lee, Chin-Chin Chen, Yuan-Ho Chen, Erl-Huei Lu |
| 2001 | ISCAS | New bit-parallel systolic multipliers for a class of GF(2m). | Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee |