Chirag Ravishankar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
4
Active years
2010–2026
Best venue rank
A
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | FCCM | PathSteiner: Improving PathFinder with Quasi-Optimal Steiner-Tree Initialization. | Shashwat Shrivastava, Luka Kuresevic, Alexandros Poupakis, Chirag Ravishankar, Dinesh Gaitonde, Stefan Nikolic, Mirjana Stojilovic |
| 2025 | FCCM | Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox. | Shashwat Shrivastava, Stefan Nikolic, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic |
| 2023 | FCCM | Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. | Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde |
| 2023 | FPGA | Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. | Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic |
| 2023 | ICCAD | IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. | Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic |
| 2019 | FPGA | Xilinx Adaptive Compute Acceleration Platform: Versal | Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer |
| 2018 | FPL | Placement Strategies for 2.5D FPGA Fabric Architectures. | Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer |
| 2012 | FPGA | EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). | Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings |
| 2012 | FPL | EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. | Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings |
| 2010 | FPGA | FPGA power reduction by guarded evaluation. | Jason Helge Anderson, Chirag Ravishankar |