| 2026 | SP | Enhancing Biosecurity Incident Response by Predicting Unknown Genetic Circuit Logic. | William Mo, Christopher A. Vaiana, Chris J. Myers |
| 2022 | VMCAI | STAMINA 2.0: Improving Scalability of Infinite-State Stochastic Model Checking. | Riley Roberts, Thakur Neupane, Lukas Buecherl, Chris J. Myers, Zhen Zhang |
| 2019 | CAV | STAMINA: STochastic Approximate Model-Checker for INfinite-State Analysis. | Thakur Neupane, Chris J. Myers, Curtis Madsen, Hao Zheng, Zhen Zhang |
| 2017 | DAC | Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited. | Vladimir Dubikhin, Chris J. Myers, Danil Sokolov, Ioannis Syranidis, Alexandre Yakovlev |
| 2017 | WSC | A brief history of COMBINE. | Chris J. Myers, Gary D. Bader, Padraig Gleeson, Martin Golebiewski, Michael Hucka, Nicolas Le Novre, David P. Nickerson, Falk Schreiber, Dagmar Waltemath |
| 2014 | FMICS | Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. | Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers |
| 2013 | DAC | Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis. | Honghuang Lin, Peng Li, Chris J. Myers |
| 2013 | FDL | A new assertion property language for analog/mixed-signal circuits. | Dhanashree Kulkarni, Andrew N. Fisher, Chris J. Myers |
| 2012 | CAV | Formal Verification of Genetic Circuits. | Chris J. Myers |
| 2012 | CIBCB | Utilizing stochastic model checking to analyze genetic circuits. | Curtis Madsen, Chris J. Myers, Nicholas Roehner, Chris Winstead, Zhen Zhang |
| 2012 | ICCAD | Modeling and design automation of biological circuits and systems. | Natasa Miskov-Zivanov, James R. Faeder, Chris J. Myers, Herbert M. Sauro |
| 2010 | ISCAS | iSSA: An incremental stochastic simulation algorithm for genetic circuits. | Chris Winstead, Curtis Madsen, Chris J. Myers |
| 2009 | ICCAD | Genetic design automation. | Chris J. Myers, Nathan A. Barker, Hiroyuki Kuwahara, Kevin R. Jones, Curtis Madsen, Nam-Phuong D. Nguyen |
| 2009 | ICCD | A new verification method for embedded systems. | Robert A. Thacker, Chris J. Myers, Kevin R. Jones, Scott Little |
| 2007 | ASPDAC | Symbolic Model Checking of Analog/Mixed-Signal Circuits. | David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda |
| 2007 | ATVA | Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. | Scott Little, David Walter, Kevin R. Jones, Chris J. Myers |
| 2007 | ATVA | Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. | David Walter, Scott Little, Chris J. Myers |
| 2007 | RECOMB | Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions. | Hiroyuki Kuwahara, Chris J. Myers |
| 2006 | ATVA | Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. | Tomohiro Yoneda, Chris J. Myers |
| 2006 | ICCAD | Verification of analog/mixed-signal circuits using labeled hybrid petri nets. | Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda |
| 2004 | ATVA | Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. | Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda |
| 2004 | ATVA | Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. | Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers |
| 2003 | ICCAD | Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. | Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda |
| 2003 | ICCD | Verification of Timed Circuits with Failure Directed Abstractions. | Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda |
| 2002 | CAV | Automatic Derivation of Timing Constraints by Failure Analysis. | Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers |
| 2002 | ISCAS | Cell library for automatic synthesis of analog error control decoders. | Jie Dai, Chris Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel |
| 2002 | PRDC | Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. | Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers |
| 2001 | ASPDAC | Timed circuits: a new paradigm for high-speed design. | Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng |
| 2001 | CAV | Automatic Abstraction for Verification of Timed Circuits and Systems. | Hao Zheng, Eric Mercer, Chris J. Myers |
| 2001 | ITW | Analog decoding of product codes. | Chris Winstead, Chris J. Myers, Christian Schlegel, Reid R. Harrison |
| 2000 | ICCAD | Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. | Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan |
| 2000 | ISCAS | Stochastic cycle period analysis in timed circuits. | Eric G. Mercer, Chris J. Myers |
| 1999 | ICCAD | Direct synthesis of timed asynchronous circuits. | Sung Tae Jung, Chris J. Myers |
| 1999 | ICCD | Architectural Synthesis of Timed Asynchronous Systems. | Brandon M. Bachman, Hao Zheng, Chris J. Myers |
| 1999 | VLSID | Timed Circuit Synthesis Using Implicit Methods. | Robert A. Thacker, Wendy Belluomini, Chris J. Myers |
| 1998 | CAV | Verification of Timed Systems Using POSETs. | Wendy Belluomini, Chris J. Myers |
| 1997 | ICASSP | An asynchronous implementation of the maxlist algorithm. | Chris J. Myers, Hao Zheng |
| 1994 | CAV | Automatic Verification of Timed Circuits. | Tomas Rokicki, Chris J. Myers |
| 1992 | ICCD | Synthesis of Timed Asynchronous Circuits. | Chris J. Myers, Teresa H.-Y. Meng |