Christopher J. Hughes
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
31
Venues
14
Active years
2001–2026
Best venue rank
A*
Where they publish
Papers
31 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | HPCA | AccelFlow: Orchestrating an On-Package Ensemble of Fine-Grained Accelerators for Microservices. | Jovan Stojkovic, Abraham Farrell, Zhangxiaowen Gong, Christopher J. Hughes, Josep Torrellas |
| 2026 | ISCA | Dorado: Clustered Hardware Cache Coherence for 1,000+ Cores. | Jovan Stojkovic, Abraham Farrell, Gerasimos Gerogiannis, Zhangxiaowen Gong, Christopher J. Hughes, Josep Torrellas |
| 2025 | HPCA | Push Multicast: A Speculative and Coherent Interconnect for Mitigating Manycore CPU Communication Bottleneck. | Jiayi Huang, Yanhua Chen, Zhe Wang, Christopher J. Hughes, Yufei Ding, Yuan Xie |
| 2025 | MICRO | Software Prefetch Multicast: Sharer-Exposed Prefetching for Bandwidth Efficiency in Manycore Processors. | Yanhua Chen, Jiong Feng, Zhe Wang, Christopher J. Hughes, Jiayi Huang |
| 2024 | SC | M3XU: Achieving High-Precision and Complex Matrix Multiplication with Low-Precision MXUs. | Dongho Ha, Yunan Zhang, Chen-Chien Kao, Christopher J. Hughes, Won Woo Ro, Hung-Wei Tseng |
| 2023 | HPCA | VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. | Geonhwa Jeong, Sana Damani, Abhimanyu Rajeshkumar Bambhaniya, Eric Qin, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna |
| 2022 | ISCA | Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. | Zhangxiaowen Gong, Houxiang Ji, Yao Yao, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas |
| 2021 | DAC | RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. | Geonhwa Jeong, Eric Qin, Ananda Samajdar, Christopher J. Hughes, Sreenivas Subramoney, Hyesoon Kim, Tushar Krishna |
| 2021 | ICS | SumMerge: an efficient algorithm and implementation for weight repetition-aware DNN inference. | Rohan Baskar Prabhakar, Sachit Kuhar, Rohit Agrawal, Christopher J. Hughes, Christopher W. Fletcher |
| 2020 | ICCAD | SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. | Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey |
| 2020 | MICRO | SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. | Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Sara S. Baghsorkhi, Josep Torrellas |
| 2019 | FCCM | T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. | Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey |
| 2017 | MICRO | Banshee: bandwidth-efficient DRAM caching via software/hardware cooperation. | Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Onur Mutlu, Srinivas Devadas |
| 2016 | HPCA | PleaseTM: Enabling transaction conflict management in requester-wins hardware transactional memory. | Sunjae Park, Milos Prvulovic, Christopher J. Hughes |
| 2015 | MICRO | IMP: indirect memory prefetcher. | Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, Srinivas Devadas |
| 2013 | SC | Location-aware cache management for many-core processors with deep cache hierarchy. | Jongsoo Park, Richard M. Yoo, Daya Shanker Khudia, Christopher J. Hughes, Daehyun Kim |
| 2013 | SC | Performance evaluation of Intel transactional synchronization extensions for high-performance computing. | Richard M. Yoo, Christopher J. Hughes, Konrad Lai, Ravi Rajwar |
| 2013 | SPAA | Locality-aware task management for unstructured parallelism: a quantitative limit study. | Richard M. Yoo, Christopher J. Hughes, Changkyu Kim, Yen-Kuang Chen, Christos Kozyrakis |
| 2011 | ISCA | Moguls: a model to explore the memory hierarchy for bandwidth improvements. | Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen |
| 2011 | ICSE | LIME: a framework for debugging load imbalance in multi-threaded execution. | Jungju Oh, Christopher J. Hughes, Guru Venkataramani, Milos Prvulovic |
| 2008 | ISCA | Atomic Vector Operations on Chip Multiprocessors. | Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Yen-Kuang Chen, Jatin Chhugani, Christopher J. Hughes, Changkyu Kim, Victor W. Lee, Anthony D. Nguyen |
| 2007 | ISCA | Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. | Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen |
| 2007 | ISCA | Carbon: architectural support for fine-grained parallelism on chip multiprocessors. | Sanjeev Kumar, Christopher J. Hughes, Anthony D. Nguyen |
| 2006 | KDD | Incremental approximate matrix factorization for speeding up support vector machines. | Gang Wu, Edward Y. Chang, Yen-Kuang Chen, Christopher J. Hughes |
| 2006 | PPoPP | Hybrid transactional memory. | Sanjeev Kumar, Michael Chu, Christopher J. Hughes, Partha Kundu, Anthony D. Nguyen |
| 2004 | ISCA | A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. | Christopher J. Hughes, Sarita V. Adve |
| 2002 | ASPLOS | Joint local and global hardware adaptations for energy. | Ruchira Sasanka, Christopher J. Hughes, Sarita V. Adve |
| 2002 | RTSS | Soft Real- Time Scheduling on Simultaneous Multithreaded Processors. | Rohit Jain, Christopher J. Hughes, Sarita V. Adve |
| 2001 | ISCA | Speculative precomputation: long-range prefetching of delinquent loads. | Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen |
| 2001 | ISCA | Variability in the execution of multimedia applications and implications for architecture. | Christopher J. Hughes, Praful Kaul, Sarita V. Adve, Rohit Jain, Chanik Park, Jayanth Srinivasan |
| 2001 | MICRO | Saving energy with architectural and frequency adaptations for multimedia applications. | Christopher J. Hughes, Jayanth Srinivasan, Sarita V. Adve |