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SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs.

Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey

VenueAICCAD
Year2020
ProceedingsICCAD

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