Zhiru Zhang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
109
Venues
22
Active years
2003–2026
Best venue rank
A*
Where they publish
- AFPGA24 papers
- A*DAC21 papers
- AICCAD16 papers
- NationalFCCM7 papers
- BASPDAC5 papers
- A*MICRO4 papers
- A*ICLR4 papers
- A*ICML4 papers
- A*ASPLOS3 papers
- A*ISCA3 papers
- A*CVPR3 papers
- A*HPCA2 papers
- ASC2 papers
- ADATE2 papers
- AISLPED2 papers
- ACGO1 paper
- A*EMNLP1 paper
- A*OSDI1 paper
- A*SIGCOMM1 paper
- BFMCAD1 paper
- A*PLDI1 paper
- NationalACSSC1 paper
Papers
109 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | CGO | Tawa: Automatic Warp Specialization for Modern GPUs with Asynchronous References. | Hongzheng Chen, Bin Fan, Alexander Collins, Bastian Hagedorn, Evghenii Gaburov, Masahiro Masuda, Matthew Brookhart, Chris Sullivan, Jason Knight, Zhiru Zhang, Vinod Grover |
| 2026 | FCCM | Reconfigurable Computing Challenge: Deploying SmolVLA Model on an AMD XDNA NPU. | Xiaoyu Liang, Elaine Cao, Chun-Ning Kao, David Lin, Jiajie Li, Zhiru Zhang |
| 2025 | ASPLOS | SmoothE: Differentiable E-Graph Extraction. | Yaohui Cai, Kaixin Yang, Chenhui Deng, Cunxi Yu, Zhiru Zhang |
| 2025 | DAC | CirSTAG: Circuit Stability Analysis on Graph-based Manifolds. | Wuxinlin Cheng, Yihang Yuan, Chenhui Deng, Ali Aghdaei, Zhiru Zhang, Zhuo Feng |
| 2025 | FPGA | ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. | Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou |
| 2025 | ICCAD | EqMap: FPGA LUT Remapping using E-Graphs. | Matthew Hofmann, Berk Gokmen, Zhiru Zhang |
| 2025 | ICCAD | e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving. | Jiaqi Yin, Zhan Song, Chen Chen, Yaohui Cai, Zhiru Zhang, Cunxi Yu |
| 2025 | MICRO | Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device. | Niansong Zhang, Wenbo Zhu, Courtney Golden, Dan Ilan, Hongzheng Chen, Christopher Batten, Zhiru Zhang |
| 2024 | ASPLOS | Slapo: A Schedule Language for Progressive Optimization of Large Deep Learning Model Training. | Hongzheng Chen, Cody Hao Yu, Shuai Zheng, Zhen Zhang, Zhiru Zhang, Yida Wang |
| 2024 | DAC | Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. | Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang |
| 2024 | EMNLP | ShadowLLM: Predictor-based Contextual Sparsity for Large Language Models. | Yash Akhauri, Ahmed F. AbouElhamayed, Jordan Dotzel, Zhiru Zhang, Alexander M. Rush, Safeen Huda, Mohamed S. Abdelfattah |
| 2024 | FPGA | A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. | Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang |
| 2024 | FPGA | Formal Verification of Source-to-Source Transformations for HLS. | Louis-Nol Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodrguez, Zhiru Zhang |
| 2024 | HPCA | LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling. | Yueying Li, Nikita Lazarev, David Koufaty, Tenny Yin, Andy Anderson, Zhiru Zhang, G. Edward Suh, Kostis Kaffes, Christina Delimitrou |
| 2024 | ICCAD | RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. | Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo |
| 2024 | ICLR | Polynormer: Polynomial-Expressive Graph Transformer in Linear Time. | Chenhui Deng, Zichao Yue, Zhiru Zhang |
| 2024 | ICLR | Exploring the Limits of Semantic Image Compression at Micro-bits per Pixel. | Jordan Dotzel, Bahaa Kotb, James Dotzel, Mohamed S. Abdelfattah, Zhiru Zhang |
| 2024 | ICML | Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. | Jordan Dotzel, Yuzong Chen, Bahaa Kotb, Sushma Prasad, Gang Wu, Sheng Li, Mohamed S. Abdelfattah, Zhiru Zhang |
| 2024 | ICML | Differentiable Combinatorial Scheduling at Scale. | Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu |
| 2024 | ISCA | Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. | Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor |
| 2024 | OSDI | Sabre: Hardware-Accelerated Snapshot Compression for Serverless MicroVMs. | Nikita Lazarev, Varun Gohil, James Tsai, Andy Anderson, Bhushan Chitlur, Zhiru Zhang, Christina Delimitrou |
| 2024 | SC | Rapid GPU-Based Pangenome Graph Layout. | Jiajie Li, Jan-Niklas Schmelzle, Yixiao Du, Simon Heumos, Andrea Guarracino, Giulia Guidi, Pjotr Prins, Erik Garrison, Zhiru Zhang |
| 2023 | DAC | Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality. | Ecenur Ustun, Cunxi Yu, Zhiru Zhang |
| 2023 | SIGCOMM | Resilient Baseband Processing in Virtualized RANs with Slingshot. | Nikita Lazarev, Tao Ji, Anuj Kalia, Daehyeok Kim, Ilias Marinos, Francis Y. Yan, Christina Delimitrou, Zhiru Zhang, Aditya Akella |
| 2022 | CVPR | PokeBNN: A Binary Pursuit of Lightweight Accuracy. | Yichi Zhang, Zhiru Zhang, Lukasz Lew |
| 2022 | DAC | GuardNN: secure accelerator architecture for privacy-preserving deep learning. | Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh |
| 2022 | DAC | Accelerator design with decoupled hardware customizations: benefits and challenges: invited. | Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Nol Pouchet, Zhiru Zhang |
| 2022 | FCCM | IMpress: Large Integer Multiplication Expression Rewriting for FPGA HLS. | Ecenur Ustun, Ismail San, Jiaqi Yin, Cunxi Yu, Zhiru Zhang |
| 2022 | FPGA | High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV. | Yixiao Du, Yuwei Hu, Zhongchun Zhou, Zhiru Zhang |
| 2022 | FPGA | RapidStream: Parallel Physical Implementation of FPGA HLS Designs. | Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong |
| 2022 | FPGA | HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. | Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang |
| 2022 | ISCA | MGX: near-zero overhead memory protection for data-intensive accelerators. | Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh |
| 2022 | ISCA | SoftVN: efficient memory protection via software-provided version numbers. | Muhammad Umar, Weizhe Hua, Zhiru Zhang, G. Edward Suh |
| 2021 | ASPDAC | Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. | Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin |
| 2021 | ASPLOS | Dagger: efficient and fast RPCs in cloud microservices with near-memory reconfigurable NICs. | Nikita Lazarev, Shaojie Xiang, Neil Adit, Zhiru Zhang, Christina Delimitrou |
| 2021 | DAC | Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC. | Yuan Zhou, Hanyu Wang, Jieming Yin, Zhiru Zhang |
| 2021 | DATE | GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation. | Jiajia Jiao, Debjit Pal, Chenhui Deng, Zhiru Zhang |
| 2021 | DATE | Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. | Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jnata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee |
| 2021 | FMCAD | Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. | Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra |
| 2021 | FPGA | AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. | Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong |
| 2021 | FPGA | FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations. | Yichi Zhang, Junhao Pan, Xinheng Liu, Hongzheng Chen, Deming Chen, Zhiru Zhang |
| 2021 | ICCAD | GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAs. | Yuwei Hu, Yixiao Du, Ecenur Ustun, Zhiru Zhang |
| 2021 | ICML | SPADE: A Spectral Method for Black-Box Adversarial Robustness Evaluation. | Wuxinlin Cheng, Chenhui Deng, Zhiqiang Zhao, Yaohui Cai, Zhiru Zhang, Zhuo Feng |
| 2020 | DAC | Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. | Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong |
| 2020 | DAC | A-QED Verification of Hardware Accelerators. | Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra |
| 2020 | FPGA | Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. | Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong |
| 2020 | HPCA | Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations. | Nitish Kumar Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David H. Albonesi, Zhiru Zhang |
| 2020 | ICCAD | SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. | Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey |
| 2020 | ICCAD | Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. | Ecenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li, Zhiru Zhang |
| 2020 | ICLR | GraphZoom: A Multi-level Spectral Approach for Accurate and Scalable Graph Embedding. | Chenhui Deng, Zhiqiang Zhao, Yongyu Wang, Zhiru Zhang, Zhuo Feng |
| 2020 | ICLR | Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. | Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang |
| 2020 | MICRO | MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product. | Nitish Kumar Srivastava, Hanchen Jin, Jie Liu, David H. Albonesi, Zhiru Zhang |
| 2020 | PLDI | Predictable accelerator design with time-sensitive affine types. | Rachit Nigam, Sachille Atapattu, Samuel Thomas, Zhijing Li, Theodore Bauer, Yuwei Ye, Apurva Koti, Adrian Sampson, Zhiru Zhang |
| 2020 | SC | FeatGraph: a flexible and efficient backend for graph neural network systems. | Yuwei Hu, Zihao Ye, Minjie Wang, Jiali Yu, Da Zheng, Mu Li, Zheng Zhang, Zhiru Zhang, Yida Wang |
| 2019 | CVPR | Building Efficient Deep Neural Networks With Unitary Group Convolutions. | Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang |
| 2019 | DAC | Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning. | Steve Dai, Zhiru Zhang |
| 2019 | DAC | Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. | Zhenghong Jiang, Hanchen Jin, G. Edward Suh, Zhiru Zhang |
| 2019 | DAC | Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set Specifications. | Gai Liu, Joseph Primmer, Zhiru Zhang |
| 2019 | DAC | Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets. | Cunxi Yu, Zhiru Zhang |
| 2019 | DAC | PRIMAL: Power Inference using Machine Learning. | Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang |
| 2019 | FCCM | T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. | Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey |
| 2019 | FCCM | LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure. | Ecenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu, Zhiru Zhang |
| 2019 | FPGA | HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. | Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang |
| 2019 | ICML | Improving Neural Network Quantization without Retraining using Outlier Channel Splitting. | Ritchie Zhao, Yuwei Hu, Jordan Dotzel, Christopher De Sa, Zhiru Zhang |
| 2019 | MICRO | Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. | Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh |
| 2018 | DAC | Reverse engineering convolutional neural networks through side-channel information leaks. | Weizhe Hua, Zhiru Zhang, G. Edward Suh |
| 2018 | FCCM | Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. | Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang |
| 2018 | FPGA | A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation. | Steve Dai, Gai Liu, Zhiru Zhang |
| 2018 | FPGA | DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only). | Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu, Guojie Luo, Zhiru Zhang |
| 2018 | FPGA | Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. | Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang |
| 2018 | ICCAD | High-level synthesis with timing-sensitive information flow enforcement. | Zhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang |
| 2017 | ACSSC | Enabling adaptive loop pipelining in high-level synthesis. | Steve Dai, Gai Liu, Ritchie Zhao, Zhiru Zhang |
| 2017 | CVPR | Binarized Convolutional Neural Networks with Separable Filters for Efficient Hardware Acceleration. | Jeng-Hau Lin, Tianwei Xing, Ritchie Zhao, Zhiru Zhang, Mani B. Srivastava, Zhuowen Tu, Rajesh K. Gupta |
| 2017 | FCCM | FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider. | Edward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael D. Hildreth, Savvas Kyriacou, Kevin Lannon, Anthony Lefeld, Anders Ryd, Louise Skinnari, Robert Stone, Charles Strohman, Zhengcheng Tao, Brian Winer, Peter Wittich, Zhiru Zhang, Margaret Zientek |
| 2017 | FPGA | Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. | Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang |
| 2017 | FPGA | A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping. | Gai Liu, Zhiru Zhang |
| 2017 | FPGA | Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. | Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang |
| 2017 | FPGA | A Parallel Bandit-Based Approach for Autotuning FPGA Compilation. | Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang |
| 2017 | FPGA | Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. | Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang |
| 2017 | FPGA | A New Approach to Automatic Memory Banking using Trace-Based Address Mining. | Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang |
| 2017 | ICCAD | Statistically certified approximate logic synthesis. | Gai Liu, Zhiru Zhang |
| 2016 | DAC | Improving high-level synthesis with decoupled data structure optimization. | Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang |
| 2015 | DAC | A reconfigurable analog substrate for highly efficient maximum flow computation. | Gai Liu, Zhiru Zhang |
| 2015 | DAC | Area-efficient pipelining for FPGA-targeted high-level synthesis. | Ritchie Zhao, Mingxing Tan, Steve Dai, Zhiru Zhang |
| 2015 | FPGA | Mapping-Aware Constrained Scheduling for LUT-Based FPGAs. | Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang |
| 2015 | ICCAD | DA Systemization of Knowledge: A Catalog of Prior Forward-Looking Initiatives. | Farinaz Koushanfar, Azalia Mirhoseini, Gang Qu, Zhiru Zhang |
| 2015 | ICCAD | ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests. | Mingxing Tan, Gai Liu, Ritchie Zhao, Steve Dai, Zhiru Zhang |
| 2014 | DAC | Flushing-Enabled Loop Pipelining for High-Level Synthesis. | Steve Dai, Mingxing Tan, Kecheng Hao, Zhiru Zhang |
| 2014 | ICCAD | Multithreaded pipeline synthesis for data-parallel kernels. | Mingxing Tan, Bin Liu, Steve Dai, Zhiru Zhang |
| 2014 | ISLPED | CASA: correlation-aware speculative adders. | Gai Liu, Ye Tao, Mingxing Tan, Zhiru Zhang |
| 2014 | MICRO | Architectural Specialization for Inter-Iteration Loop Dependence Patterns. | Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang, Christopher Batten |
| 2013 | ICCAD | SDC-based modulo scheduling for pipeline synthesis. | Zhiru Zhang, Bin Liu |
| 2010 | FPGA | Bit-level optimization for high-level synthesis and FPGA-based acceleration. | Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong |
| 2009 | FCCM | Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. | Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou |
| 2009 | FPGA | Revisiting bitwidth optimizations. | Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou |
| 2009 | ICCAD | Scheduling with soft constraints. | Jason Cong, Bin Liu, Zhiru Zhang |
| 2009 | ISLPED | Behavior-level observability don't-cares and application to low-power behavioral synthesis. | Jason Cong, Bin Liu, Zhiru Zhang |
| 2008 | ASPDAC | Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. | Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang |
| 2008 | ASPDAC | Scheduling with integer time budgeting for low-power optimization. | Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong |
| 2007 | ASPDAC | High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. | Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang |
| 2006 | DAC | Behavior and communication co-optimization for systems with sequential communication media. | Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang |
| 2006 | DAC | An efficient and versatile scheduling algorithm based on SDC formulation. | Jason Cong, Zhiru Zhang |
| 2005 | ASPDAC | Bitwidth-aware scheduling and binding in high-level synthesis. | Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng |
| 2005 | FPGA | Instruction set extension with shadow registers for configurable processors. | Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang |
| 2005 | ICCAD | Architecture and compilation for data bandwidth improvement in configurable embedded processors. | Jason Cong, Guoling Han, Zhiru Zhang |
| 2004 | DAC | Architecture-level synthesis for automatic interconnect pipelining. | Jason Cong, Yiping Fan, Zhiru Zhang |
| 2004 | FPGA | Application-specific instruction generation for configurable processor architectures. | Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang |
| 2003 | ICCAD | Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. | Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang |
| 2003 | ICCAD | Gradual Relaxation Techniques with Applications to Behavioral Synthesis. | Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong |