Yi-Hsiang Lai
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
12
Venues
5
Active years
2014–2026
Best venue rank
A*
Where they publish
Papers
12 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | EuroSys | AdaServe: Accelerating Multi-SLO LLM Serving with SLO-Customized Speculative Decoding. | Zikun Li, Zhuofu Chen, Remi Delacourt, Gabriele Oliaro, Zeyu Wang, Qinghan Chen, Shuhuai Lin, April Yang, Zhihao Zhang, Zhuoming Chen, Yi-Hsiang Lai, Xinhao Cheng, Xupeng Miao, Zhihao Jia |
| 2024 | ISSTA | Automated Deep Learning Optimization via DSL-Based Source Code Transformation. | Ruixin Wang, Minghai Lu, Cody Hao Yu, Yi-Hsiang Lai, Tianyi Zhang |
| 2022 | DAC | Accelerator design with decoupled hardware customizations: benefits and challenges: invited. | Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Nol Pouchet, Zhiru Zhang |
| 2022 | FPGA | HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. | Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang |
| 2020 | ICCAD | SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. | Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey |
| 2019 | FPGA | HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. | Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang |
| 2018 | FPGA | Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. | Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang |
| 2016 | ICCAD | Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. | Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang |
| 2015 | ICCAD | Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. | Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang |
| 2015 | ICCAD | A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. | Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang |
| 2015 | ICCAD | SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. | Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang |
| 2014 | DAC | Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. | Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang |