Chuck Haymes
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2012–2023
Best venue rank
A
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | FPGA | Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation. | Bharat Sukhwani, Mohit Kapur, Alda Ohmacht, Liran Schour, Martin Ohmacht, Chris Ward, Chuck Haymes, Sameh W. Asaad |
| 2014 | SC | Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100 Speedup in Time-to-Solution and ~100, 000 Reduction in Energy-to-Solution. | Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc Gonzlez Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha |
| 2012 | FPGA | A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. | Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, Jos A. Tierno |
| 2012 | FPGA | Efficient in-system RTL verification and debugging using FPGAs (abstract only). | Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad |