| 2025 | QCE | A Lazy Resynthesis Approach for Simultaneous T Gate and Two-Qubit Gate Optimization of Quantum Circuits. | Mu-Te Lau, Hsiang-Chun Yang, Hsin-Yu Chen, Chung-Yang Huang |
| 2017 | CVPR | Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. | Kuan-Lun Tseng, Yen-Liang Lin, Winston H. Hsu, Chung-Yang Huang |
| 2012 | ASPDAC | A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints. | Shihheng Tsai, Man-Yu Li, Chung-Yang Huang |
| 2012 | DATE | Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. | Kai-Fu Tang, Po-Kai Huang, Chun-Nan Chou, Chung-Yang Huang |
| 2011 | ASPDAC | A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. | Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang |
| 2011 | ASPDAC | SoC HW/SW verification and validation. | Chung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang, Ting-Mao Chang |
| 2011 | DATE | Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. | Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin |
| 2011 | ICCAD | Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques. | Bo-Han Wu, Chun-Ju Yang, Chia-Cheng Tso, Chung-Yang Huang |
| 2011 | ICCAD | Property-specific sequential invariant extraction for SAT-based unbounded model checking. | Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang Huang |
| 2010 | ASPDAC | Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling. | Kuen-Huei Lin, Siao-Jie Cai, Chung-Yang Huang |
| 2010 | ASPDAC | A unified multi-corner multi-mode static timing analysis engine. | Jing-Jia Nian, Shihgeng Tsai, Chung-Yang Huang |
| 2010 | ASPDAC | Automatic constraint generation for guided random simulation. | Hu-Hsi Yeh, Chung-Yang Huang |
| 2010 | ICCAD | Formal deadlock checking on high-level SystemC designs. | Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang Huang |
| 2010 | ICCAD | A robust functional ECO engine by SAT proof minimization and interpolation techniques. | Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang |
| 2009 | ASPDAC | SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. | Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang |
| 2009 | DAC | A false-path aware formal static timing analyzer considering simultaneous input transitions. | Shihheng Tsai, Chung-Yang Huang |
| 2009 | ICCAD | Interpolant generation without constructing resolution graph. | Chih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang |
| 2008 | DATE | Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. | Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo |
| 2007 | DATE | QuteSAT: a robust circuit-based SAT solver for complex circuit structure. | Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang |
| 2007 | ICCAD | Scalable exploration of functional dependency by interpolation and incremental SAT solving. | Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko |
| 2000 | DAC | Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. | Chung-Yang Huang, Kwang-Ting Cheng |
| 2000 | ITC | Static property checking using ATPG vs. BDD techniques. | Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng |