Clarence Tam
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2004–2006
Best venue rank
A
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | ITC | Massively Parallel Validation of High-Speed Serial Interfaces using Compact Instrument Modules. | Mohamed Hafed, Daniel Watkins, Clarence Tam, Bardia Pishdad |
| 2004 | ITC | A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing. | Mohamed M. Hafed, Antonio H. Chan, Geoffrey D. Duerden, Bardia Pishdad, Clarence Tam, Sbastien Laberge, Gordon W. Roberts |