| 2003 | ASPDAC | Floorplanning with power supply noise avoidance. | Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong |
| 2003 | ASPDAC | A fast and accurate method for interconnect current calculation. | Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan |
| 2003 | DAC | Blade and razor: cell and interconnect delay analysis using current-based models. | John F. Croix, D. F. Wong |
| 2003 | DATE | Global Wire Bus Configuration with Minimum Delay Uncertainty. | Li-Da Huang, Hung-Ming Chen, D. F. Wong |
| 2003 | FPGA | Wire type assignment for FPGA routing. | Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun |
| 2002 | DAC | Floorplanning with alignment and performance constraints. | Xiaoping Tang, D. F. Wong |
| 2002 | DAC | An algorithm for integrated pin assignment and buffer planning. | Hua Xiang, D. F. Wong, Xiaoping Tang |
| 2002 | DATE | Maze Routing with Buffer Insertion under Transition Time Constraints. | Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao |
| 2002 | DATE | A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. | Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu |
| 2002 | FPGA | Incremental reconfiguration of multi-FPGA systems. | K. K. Lee, D. F. Wong |
| 2002 | ICCAD | Shaping interconnect for uniform current density. | Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao |
| 2002 | ICCAD | On mask layout partitioning for electron projection lithography. | Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong |
| 2002 | ICCAD | ECO algorithms for removing overlaps between power rails and signal wires. | Hua Xiang, Kai-Yuan Chao, D. F. Wong |
| 2001 | ASPDAC | A fast and accurate delay estimation method for buffered interconnects. | Youxin Gao, D. F. Wong |
| 2001 | ASPDAC | Memory-efficient interconnect optimization. | Minghorng Lai, D. F. Wong |
| 2001 | ASPDAC | Integrated power supply planning and floorplanning. | I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong |
| 2001 | ASPDAC | FAST-SP: a fast algorithm for block placement based on sequence pair. | Xiaoping Tang, D. F. Wong |
| 2001 | DATE | A graph based algorithm for optimal buffer insertion under accurate delay models. | Youxin Gao, D. F. Wong |
| 2001 | DATE | Slicing tree is a complete floorplan representation. | Minghorng Lai, D. F. Wong |
| 2001 | FPGA | LRoute: a delay minimal router for hierarchical CPLDs. | K. K. Lee, D. F. Wong |
| 2001 | ICCAD | A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. | Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong |
| 2001 | ICCAD | An Algorithm for Simultaneous Pin Assignment and Routing. | Hua Xiang, Xiaoping Tang, D. F. Wong |
| 2000 | DAC | Maze routing with buffer insertion and wiresizing. | Minghorng Lai, D. F. Wong |
| 2000 | DAC | Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. | Ruiqi Tian, D. F. Wong, Robert Boone |
| 2000 | DAC | Optimal low power X OR gate decomposition. | Hai Zhou, D. F. Wong |
| 2000 | DATE | Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. | Youxin Gao, D. F. Wong |
| 2000 | DATE | Meeting Delay Constraints in DSM by Minimal Repeater Insertion. | I-Min Liu, Adnan Aziz, D. F. Wong |
| 2000 | DATE | Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. | Xiaoping Tang, D. F. Wong, Ruiqi Tian |
| 1999 | ASPDAC | Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. | Youxin Gao, D. F. Wong |
| 1999 | ASPDAC | Slicing Floorplans with Boundary Constraint. | Fung Yu Young, D. F. Wong |
| 1999 | DAC | Error Bounded Pad Approximation via Bilinear Conformal Transformation. | Chung-Ping Chen, D. F. Wong |
| 1999 | DAC | Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. | Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz |
| 1999 | FPGA | Circuit Partitioning for Dynamically Reconfigurable FPGAs. | Huiqun Liu, D. F. Wong |
| 1999 | ICCAD | Integrated floorplanning and interconnect planning. | Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani |
| 1999 | ICCAD | A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. | Huiqun Liu, D. F. Wong |
| 1999 | ICCAD | Advances in transistor timing, simulation, and optimization (tutorial abstract). | Jacob White, Jacob Avidan, Ibrahim Abe M. Elfadel, D. F. Wong |
| 1999 | ICCD | An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. | K. K. Lee, D. F. Wong |
| 1999 | ICCD | An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. | I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou |
| 1999 | ISCAS | A fast hypergraph minimum cut algorithm. | Wai-Kei Mak, D. F. Wong |
| 1998 | DAC | Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. | Madhukar R. Korupolu, K. K. Lee, D. F. Wong |
| 1998 | DAC | Global Routing with Crosstalk Constraints. | Hai Zhou, D. F. Wong |
| 1998 | DATE | A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. | Chris C. N. Chu, D. F. Wong |
| 1998 | FPGA | Circuit Partitioning with Complex Resource Constraints in FPGAs. | Huiqun Liu, Kai Zhu, D. F. Wong |
| 1998 | FPGA | Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). | Wai-Kei Mak, D. F. Wong |
| 1998 | ICCAD | Graph matching-based algorithms for FPGA segmentation design. | Yao-Wen Chang, Jai-Ming Lin, D. F. Wong |
| 1998 | ICCAD | Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. | Chung-Ping Chen, Chris C. N. Chu, D. F. Wong |
| 1998 | ICCAD | Shaping a VLSI wire to minimize delay using transmission line model. | Youxin Gao, D. F. Wong |
| 1998 | ICCAD | Network flow based circuit partitioning for time-multiplexed FPGAs. | Huiqun Liu, D. F. Wong |
| 1998 | ICCAD | Slicing floorplans with pre-placed modules. | Fung Yu Young, D. F. Wong |
| 1998 | ICCD | Integrated partitioning and scheduling for hardware/software co-design. | Huiqun Liu, D. F. Wong |
| 1998 | ICCD | Performance-driven board-level routing for FPGA-based logic emulation. | Wai-Kei Mak, D. F. Wong |
| 1998 | ICCD | Timing-driven routing for symmetrical-array-based FPGAs. | Kai Zhu, Yao-Wen Chang, D. F. Wong |
| 1997 | DAC | Optimal Wire-Sizing Function with Fringing Capacitance Consideration. | Chung-Ping Chen, D. F. Wong |
| 1997 | DAC | A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. | John F. Croix, D. F. Wong |
| 1997 | ICCAD | A new approach to simultaneous buffer insertion and wire sizing. | Chris C. N. Chu, D. F. Wong |
| 1997 | ICCAD | Optimal shape function for a bi-directional wire under Elmore delay model. | Youxin Gao, D. F. Wong |
| 1997 | ICCAD | An exact gate decomposition algorithm for low-power technology mapping. | Hai Zhou, D. F. Wong |
| 1997 | ICCD | Channel Segmentation Design for Symmentrical FPGAs. | Wai-Kei Mak, D. F. Wong |
| 1997 | ICCD | Clustering and Load Balancing for Buffered Clock Tree Synthesis. | Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi |
| 1997 | ICCD | On the Construction of Universal Series-Parallel Functions for Logic Module Design. | Fung Yu Young, D. F. Wong |
| 1997 | ICCD | Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. | Hai Zhou, D. F. Wong |
| 1996 | DAC | Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. | Chung-Ping Chen, Yao-Wen Chang, D. F. Wong |
| 1996 | DAC | Optimal Wire-Sizing Formular Under the Elmore Delay Model. | Chung-Ping Chen, Yao-Ping Chen, D. F. Wong |
| 1996 | DAC | Delay Minimal Decomposition of Multiplexers in Technology Mapping. | Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy |
| 1996 | DATE | An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion. | Y. P. Chen, D. F. Wong |
| 1996 | FPGA | Universal Switch-Module Design for Symmetric-Array-Based FPGAs. | Yao-Wen Chang, D. F. Wong, C. K. Wong |
| 1996 | FPGA | Universal Logic Modules for Series-Parallel Functions. | Shashidhar Thakur, D. F. Wong |
| 1996 | ICCAD | Optimal non-uniform wire-sizing under the Elmore delay model. | Chung-Ping Chen, Hai Zhou, D. F. Wong |
| 1996 | ICCAD | Minimum replication min-cut partitioning. | Wai-Kei Mak, D. F. Wong |
| 1996 | ICCAD | An optimal algorithm for river routing with crosstalk constraints. | Hai Zhou, D. F. Wong |
| 1996 | ICCD | Multiplexor Network Generation in High Level Synthesis. | Yung-Ming Fang, D. F. Wong |
| 1995 | DAC | On Optimal Board-Level Routing for FPGA-Based Logic Emulation. | Wai-Kei Mak, D. F. Wong |
| 1995 | DATE | Circuit clustering for delay minimization under area and pin constraints. | Honghua Yang, D. F. Wong |
| 1995 | FPGA | On Designing ULM-based FPGA Logic Modules. | Shashidhar Thakur, D. F. Wong |
| 1995 | ICCAD | Signal integrity optimization on the pad assignment for high-speed VLSI design. | Kai-Yuan Chao, D. F. Wong |
| 1995 | ICCAD | Board-level multi-terminal net routing for FPGA-based logic emulation. | Wai-Kei Mak, D. F. Wong |
| 1995 | ICCAD | New algorithms for min-cut replication in partitioned circuits. | Hannah Honghua Yang, D. F. Wong |
| 1995 | ICCD | FPGA global routing based on a new congestion metric. | Yao-Wen Chang, D. F. Wong, C. K. Wong |
| 1995 | ICCD | Design and analysis of FPGA/FPIC switch modules. | Yao-Wen Chang, D. F. Wong, C. K. Wong |
| 1995 | ICCD | Thermal placement for high-performance multichip modules. | Kai-Yuan Chao, D. F. Wong |
| 1995 | ICCD | Simultaneous area and delay minimum K-LUT mapping for K-exact networks. | Shashidhar Thakur, D. F. Wong |
| 1995 | ISCAS | Floorplanning for Low Power Designs. | Kai-Yuan Chao, D. F. Wong |
| 1995 | ISCAS | A Graph Theoretic Approach to Feed-Through Pin Assignment. | Yao-Ping Chen, D. F. Wong |
| 1995 | ISCAS | An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. | Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong |
| 1994 | DAC | Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. | Kai Zhu, D. F. Wong |
| 1994 | DAC | Clock Skew Minimization During FPGA Placement. | Kai Zhu, D. F. Wong |
| 1994 | ICCAD | A new global routing algorithm for FPGAs. | Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong |
| 1994 | ICCAD | Layer assignment for high-performance multi-chip modules. | Kai-Yuan Chao, D. F. Wong |
| 1994 | ICCAD | Simultaneous functional-unit binding and floorplanning. | Yung-Ming Fang, D. F. Wong |
| 1994 | ICCAD | Efficient network flow based min-cut balanced partitioning. | Honghua Yang, D. F. Wong |
| 1994 | ICCAD | Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. | Hannah Honghua Yang, D. F. Wong |
| 1994 | ICCD | On Retiming for FPGA Logic Module Minimization. | Yao-Ping Chen, D. F. Wong |
| 1994 | ISCAS | Over-the-Cell Routing with Cell Orientations Consideration. | T. W. Her, D. F. Wong |
| 1993 | DAC | HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. | Glenn G. Lai, Donald S. Fussell, D. F. Wong |
| 1993 | DAC | Optimal Clustering for Delay Minimization. | Rajmohan Rajaraman, D. F. Wong |
| 1993 | ICCAD | Switch module design with application to two-dimensional segmentation design. | Kai Zhu, D. F. Wong, Yao-Wen Chang |
| 1993 | ISCAS | On optimal approximation of orthogonal polygons. | Yao-Ping Chen, D. F. Wong |
| 1993 | ISCAS | A Graph Partitioning Problem for Multiple-chip Design. | Yao-Ping Chen, Ting-Chi Wang, D. F. Wong |
| 1992 | DAC | A Graph Theoretic Technique to Speed up Floorplan Area Optimization. | Ting-Chi Wang, D. F. Wong |
| 1992 | ICCAD | On channel segmentation design for row-based FPGAs. | Kai Zhu, D. F. Wong |
| 1992 | ICCD | Channel Density Minimization by Pin Permutation. | Yang Cai, D. F. Wong |
| 1991 | DAC | On Minimizing the Number of L-Shaped Channels. | Yang Cai, D. F. Wong |
| 1991 | DAC | A General Multi-Layer Area Router. | Mohankumar Guruswamy, D. F. Wong |
| 1991 | ICCAD | Minimizing Channel Density by Shifting Blocks and Terminals. | Yang Cai, D. F. Wong |
| 1991 | ICCAD | Optimal Module Implementation and Its Application to Transistor Placement. | T. W. Her, D. F. Wong |
| 1991 | ICCD | On the Manisfestation of Faults to Errors in Signature Analysis. | John C. Chan, Baxter F. Womack, D. F. Wong |
| 1991 | ICCD | Area Optimization for Higher Order Hierarchical Floorplans. | Khe-Sing The, D. F. Wong |
| 1990 | DAC | A Channel/Switchbox Definition Algorithm for Building-Block Layout. | Yang Cai, D. F. Wong |
| 1990 | DAC | An Optimal Algorithm for Floorplan Area Optimization. | Ting-Chi Wang, D. F. Wong |
| 1990 | ICCAD | An Optimal Channel Pin Assignment Algorithm. | Yang Cai, D. F. Wong |
| 1990 | ICCAD | Topological Routing Using Geometric Information. | Shinichiro Haruyama, D. F. Wong, Donald S. Fussell |
| 1990 | ICCAD | Optimal Orientations of Transistor Chains. | T. W. Her, D. F. Wong, T. H. Freeman |
| 1989 | DAC | VIA Minimization by Layout Modification. | Khe-Sing The, D. F. Wong, Jason Cong |
| 1989 | DAC | Efficient Floorplan Area Optimization. | D. F. Wong, P. S. Sakhamuri |
| 1989 | ICCAD | An algorithm for hierarchical floorplan design. | D. F. Wong, Khe-Sing The |
| 1988 | DAC | How to Obtain More Compactable Channel Routing Solutions. | Jingsheng Cong, D. F. Wong |
| 1987 | DAC | Array Optimization for VLSI Synthesis. | D. F. Wong, C. L. Liu |
| 1986 | DAC | A new algorithm for floorplan design. | D. F. Wong, C. L. Liu |