Daniel Auvergne
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
4
Active years
1994–2005
Best venue rank
A
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | DATE | Low Power Oriented CMOS Circuit Optimization Protocol. | Alexandre Verle, Xavier Michel, Nadine Azmard, Philippe Maurine, Daniel Auvergne |
| 2004 | ISCAS | Delay bound based CMOS gate sizing technique. | Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azmard, Daniel Auvergne |
| 2002 | DATE | Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. | Wenceslas Rahajandraibe, Christian Dufaza, Daniel Auvergne, Bruno Cialdella, Bernard Majoux, Vivek Chowdhury |
| 2001 | ISCAS | Delay bound determination for timing closure satisfaction. | Nadine Azmard, M. Aline, Daniel Auvergne |
| 2001 | ISCAS | Output transition time modeling of CMOS structures. | Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne |
| 1998 | DATE | Temperature Effect on Delay for Low Voltage Applications. | Jean Michel Daga, E. Ottaviano, Daniel Auvergne |
| 1997 | DATE | Internal power modelling and minimization in CMOS inverters. | S. Turgis, Jean Michel Daga, Josep M. Portal, Daniel Auvergne |
| 1996 | DATE | Design and selection of buffers for minimum power-delay product. | S. Turgis, Nadine Azmard, Daniel Auvergne |
| 1995 | ISLPED | Explicit evaluation of short circuit power dissipation for CMOS logic structures. | S. Turgis, Nadine Azmard, Daniel Auvergne |
| 1994 | FPL | Influence of Locig Block Layout Architecture on FPGA Performance. | Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne |