| 2026 | CCGRID | CroSatFL: Energy-Efficient Federated Learning with Cross-Aggregation for Satellite Edge Computing. | Nan Yang, Bahman Javadi, Rodrigo Neves Calheiros, David Boland, Philip Leong |
| 2026 | HPCA | TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification. | Yang Zhong, Haoran Wu, Xueqi Li, Sa Wang, David Boland, Yungang Bao, Kan Shi |
| 2025 | ASPDAC | Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration. | Zijian Jiang, Keran Zheng, David Boland, Yungang Bao, Kan Shi |
| 2025 | FPGA | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. | Shuoxiang Xu, Zijian Jiang, Yuxin Zhang, David Boland, Yungang Bao, Kan Shi |
| 2024 | ASPLOS | Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration. | Ziqing Zhang, Weijie Weng, Yaning Li, Lijia Cai, Haoyu Wang, David Boland, Yungang Bao, Kan Shi |
| 2024 | FPL | PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs. | Binglei Lou, Richard Rademacher, David Boland, Philip H. W. Leong |
| 2023 | FPGA | Single-Batch CNN Training using Block Minifloats on FPGAs. | Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong |
| 2023 | FPGA | ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. | Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao |
| 2023 | ICCAD | BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer Learning. | Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong, Cheng Zhuo |
| 2023 | ICPADS | On-Board Federated Learning in Orbital Edge Computing. | Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler |
| 2023 | UCC | Performance Analysis of Federated Learning in Orbital Edge Computing. | Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler |
| 2021 | FPGA | MLBlocks: FPGA Blocks for Machine Learning Applications. | Seyedramin Rasoulinezhad, David Boland, Philip H. W. Leong |
| 2021 | ICLR | A Block Minifloat Representation for Training Deep Neural Networks. | Sean Fox, Seyedramin Rasoulinezhad, Julian Faraone, David Boland, Philip H. W. Leong |
| 2020 | FPGA | LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. | Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong |
| 2018 | FPGA | FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method. | Sean Fox, David Boland, Philip Heng Wai Leong |
| 2018 | FPL | Customizing Low-Precision Deep Neural Networks for FPGAs. | Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland |
| 2018 | ISCAS | Real-time FPGA-based Anomaly Detection for Radio Frequency Signals. | Duncan J. M. Moss, David Boland, Peyam Pourbeik, Philip Heng Wai Leong |
| 2017 | FPL | Dynamic bitwidth assignment for efficient dot products. | Simon Joel Schmidt, David Boland |
| 2017 | FPL | FPGA acceleration of multilevel ORB feature extraction for computer vision. | Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond |
| 2016 | FPGA | Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination. | David Boland |
| 2014 | DAC | Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. | Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides |
| 2013 | FCCM | Accuracy-Performance Tradeoffs on an FPGA through Overclocking. | Kan Shi, David Boland, George A. Constantinides |
| 2013 | FPGA | Word-length optimization beyond straight line code. | David Boland, George A. Constantinides |
| 2013 | ISCAS | Overclocking datapath for latency-error tradeoff. | Kan Shi, David Boland, George A. Constantinides |
| 2012 | FPGA | A scalable approach for automated precision analysis. | David Boland, George A. Constantinides |
| 2010 | FCCM | Automated Precision Analysis: A Polynomial Algebraic Approach. | David Boland, George A. Constantinides |
| 2008 | FPL | An FPGA-based implementation of the MINRES algorithm. | David Boland, George A. Constantinides |