Skip to content

David E. Lackey

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

7

Venues

5

Active years

2002–2010

Best venue rank

A*

Where they publish

Papers

7 indexed papers, newest first.

YearVenueTitleAuthors
2010ITCLow cost at-speed testing using On-Product Clock Generation compatible with test compression.Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise
2007ICCADVariation-aware performance verification using at-speed structural test and statistical timing.Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah
2007VTSAn Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor, Mike Degregorio, Steven F. Oakland
2006ITCEfficient Latch and Clock Structures for System-on-Chip Test Flexibility.David E. Lackey
2003ASPDACIBM's 50 Million gate ASICs.Jrgen Koehl, David E. Lackey, George W. Doerre
2003DACDesigning mega-ASICs in nanogate technologies.David E. Lackey, Paul S. Zuchowski, Jrgen Koehl
2002ICCADManaging power and performance for System-on-Chip designs using Voltage Islands.David E. Lackey, Paul S. Zuchowski, Thomas R. Bednar, Douglas W. Stout, Scott W. Gould, John M. Cohn