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David H. Albonesi

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

37

Venues

13

Active years

1998–2020

Best venue rank

A*

Where they publish

Papers

37 indexed papers, newest first.

YearVenueTitleAuthors
2020HPCATensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations.Nitish Kumar Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David H. Albonesi, Zhiru Zhang
2020MICROCuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores.Neeraj Kulkarni, Gonzalo Gonzalez-Pumariega, Amulya Khurana, Christine A. Shoemaker, Christina Delimitrou, David H. Albonesi
2020MICROMatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product.Nitish Kumar Srivastava, Hanchen Jin, Jie Liu, David H. Albonesi, Zhiru Zhang
2019FCCMT2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations.Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey
2017HPCADynamic GPGPU Power Management Using Adaptive Model Predictive Control.Abhinandan Majumdar, Leonardo Piga, Indrani Paul, Joseph L. Greathouse, Wei Huang, David H. Albonesi
2017IJCNNDeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks.Tayyar Rzayev, Saber Moradi, David H. Albonesi, Rajit Manohar
2017ISPASSToolbox for exploration of energy-efficient event processors for human-computer interaction.Tayyar Rzayev, David H. Albonesi, Franois Guimbretire, Rajit Manohar, Jaeyeon Kihm
2013ISCAFlicker: a dynamically adaptive architecture for power limited multicore systems.Paula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker
2012SENSYSEnergy-aware meeting scheduling algorithms for smart buildings.Abhinandan Majumdar, David H. Albonesi, Pradip Bose
2010DSDAdaptive Cache Memories for SMT Processors.Sonia Lpez, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, Jos Ignacio Hidalgo
2010MICROReMAP: A Reconfigurable Heterogeneous Multicore Architecture.Matthew A. Watkins, David H. Albonesi
2009ISCAPhastlane: a rapid transit optical routing network.Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi
2008DSNScheduling algorithms for unpredictably heterogeneous CMP architectures.Jonathan A. Winter, David H. Albonesi
2008FPLShared reconfigurable architectures for CMPS.Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi
2006ISCASLocalized microarchitecture-level voltage management.Yongkang Zhu, David H. Albonesi
2006ISLPEDSynergistic temperature and energy management in GALS processor architectures.Yongkang Zhu, David H. Albonesi
2006MICROLeveraging Optical Technology in Future Bus-based Chip Multiprocessors.Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, Jos F. Martnez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
2005ISCASElectrical and optical on-chip interconnects in scaled microprocessors.Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
2005ISPASSPartitioning Multi-Threaded Processors with a Large Number of Threads.Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas
2005ISPASSA High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity.Yongkang Zhu, David H. Albonesi, Alper Buyuktosunoglu
2005WCAEQUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education.Gregory J. Briggs, Edwin J. Tan, Nicholas A. Nelson, David H. Albonesi
2004MICRODynamically Trading Frequency for Complexity in a GALS Microprocessor.Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
2003HPCADynamic Data Dependence Tracking and its Application to Branch Prediction.Lei Chen, Steve Dropsho, David H. Albonesi
2003HPCAFront-End Policies for Improved Issue Efficiency in SMT Processors.Ali El-Moursy, David H. Albonesi
2003ISCADynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors.Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2003ISCAEnergy Efficient Co-Adaptive Instruction Fetch and Issue.Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
2003ISCAProfile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor.Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho
2002HPCAEnergy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott
2002ISLPEDTradeoffs in power-efficient issue queue design.Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster
2002ISLPEDA microarchitectural-level step-power analysis tool.Wael El-Essawy, David H. Albonesi, Balaram Sinharoy
2002MICROManaging static leakage energy in microprocessor functional units.Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman
2002MICRODynamic frequency and voltage control for a multiple clock domain microarchitecture.Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott
2001ISCADynamically allocating processor resources between nearby and distant ILP.Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2001MICROReducing the complexity of the register file in dynamic superscalar processors.Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
2000MICROMemory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
1999MICROSelective Cache Ways: On-Demand Cache Resource Allocation.David H. Albonesi
1998ISCADynamic IPC/Clock Rate Optimization.David H. Albonesi