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David M. Brooks

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

76

Venues

19

Active years

1999–2021

Best venue rank

A*

Where they publish

Papers

76 indexed papers, newest first.

YearVenueTitleAuthors
2021ISLPEDApplication-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories.Mohammad Mehdi Sharifi, Lillian Pentecost, Ramin Rajaei, Arman Kazemi, Qiuwen Lou, Gu-Yeon Wei, David M. Brooks, Kai Ni, X. Sharon Hu, Michael T. Niemier, Marco Donato
2020ISLPEDA comprehensive methodology to determine optimal coherence interfaces for many-accelerator SoCs.Kshitij Bhardwaj, Marton Havasi, Yuan Yao, David M. Brooks, Jos Miguel Hernndez-Lobato, Gu-Yeon Wei
2018DACAres: a framework for quantifying the resilience of deep neural networks.Brandon Reagen, Udit Gupta, Lillian Pentecost, Paul N. Whatmough, Sae Kyu Lee, Niamh Mulholland, David M. Brooks, Gu-Yeon Wei
2018HPCAApplied Machine Learning at Facebook: A Datacenter Infrastructure Perspective.Kim M. Hazelwood, Sarah Bird, David M. Brooks, Soumith Chintala, Utku Diril, Dmytro Dzhulgakov, Mohamed Fawzy, Bill Jia, Yangqing Jia, Aditya Kalro, James Law, Kevin Lee, Jason Lu, Pieter Noordhuis, Misha Smelyanskiy, Liang Xiong, Xiaodong Wang
2017ACSSCSub-uJ deep neural networks for embedded applications.Paul N. Whatmough, Sae Kyu Lee, Gu-Yeon Wei, David M. Brooks
2017ASPLOSMallacc: Accelerating Memory Allocation.Svilen Kanev, Sam Likun Xi, Gu-Yeon Wei, David M. Brooks
2017DACIvory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators.An Zou, Jingwen Leng, Yazhou Zu, Tao Tong, Vijay Janapa Reddi, David M. Brooks, Gu-Yeon Wei, Xuan Zhang
2017ICCDVery Low Voltage (VLV) Design.Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel J. Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler
2017ICCDApplications of Deep Neural Networks for Ultra Low Power IoT.Sreela Kodali, Patrick Hansen, Niamh Mulholland, Paul N. Whatmough, David M. Brooks, Gu-Yeon Wei
2017ISCASUsing dynamic dependence analysis to improve the quality of high-level synthesis designs.Rafael Garibotti, Brandon Reagen, Yakun Sophia Shao, Gu-Yeon Wei, David M. Brooks
2017ISLPEDA case for efficient accelerator design space exploration via Bayesian optimization.Brandon Reagen, Jos Miguel Hernndez-Lobato, Robert Adolf, Michael A. Gelbart, Paul N. Whatmough, Gu-Yeon Wei, David M. Brooks
2016ISCAMinerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators.Brandon Reagen, Paul N. Whatmough, Robert Adolf, Saketh Rama, Hyunkwang Lee, Sae Kyu Lee, Jos Miguel Hernndez-Lobato, Gu-Yeon Wei, David M. Brooks
2016MICROCo-designing accelerators and SoC interfaces using gem5-Aladdin.Yakun Sophia Shao, Sam Likun Xi, Vijayalakshmi Srinivasan, Gu-Yeon Wei, David M. Brooks
2015CGOHELIX-UP: relaxing program semantics to unleash parallelization.Simone Campanoni, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks
2015HPCAQuantifying sources of error in McPAT and potential impacts on architectural studies.Sam Likun Xi, Hans M. Jacobson, Pradip Bose, Gu-Yeon Wei, David M. Brooks
2015ISCAProfiling a warehouse-scale computer.Svilen Kanev, Juan Pablo Darago, Kim M. Hazelwood, Parthasarathy Ranganathan, Tipp Moseley, Gu-Yeon Wei, David M. Brooks
2014ICCDMulti-accelerator system development with the ShrinkFit acceleration framework.Michael J. Lyons, Gu-Yeon Wei, David M. Brooks
2014ISCAHELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs.Simone Campanoni, Kevin Brownell, Svilen Kanev, Timothy M. Jones, Gu-Yeon Wei, David M. Brooks
2014ISCAAladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures.Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei, David M. Brooks
2013ISLPEDQuantifying acceleration: Power/performance trade-offs of application kernels in hardware.Brandon Reagen, Yakun Sophia Shao, Gu-Yeon Wei, David M. Brooks
2013ISLPEDEnergy characterization and instruction-level energy model of Intel's Xeon Phi processor.Yakun Sophia Shao, David M. Brooks
2013ISLPEDCharacterizing and evaluating voltage noise in multi-core near-threshold processors.Xuan Zhang, Tao Tong, Svilen Kanev, Sae Kyu Lee, Gu-Yeon Wei, David M. Brooks
2013ISPASSISA-independent workload characterization and its implications for specialized architectures.Yakun Sophia Shao, David M. Brooks
2012CGOHELIX: automatic parallelization of irregular programs for chip multiprocessing.Simone Campanoni, Timothy M. Jones, Glenn H. Holloway, Vijay Janapa Reddi, Gu-Yeon Wei, David M. Brooks
2012DACThe HELIX project: overview and directions.Simone Campanoni, Timothy M. Jones, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks
2012ISLPEDXIOSim: power-performance modeling of mobile x86 cores.Svilen Kanev, Gu-Yeon Wei, David M. Brooks
2012ISLPEDEvaluation of voltage stacking for near-threshold multicore computing.Sae Kyu Lee, David M. Brooks, Gu-Yeon Wei
2011ASPDACThe alarms project: A hardware/software approach to addressing parameter variations.David M. Brooks
2011DACDimetrodon: processor-level preventive thermal management via idle cycle injection.Peter Bailis, Vijay Janapa Reddi, Sanjay Gandhi, David M. Brooks, Margo I. Seltzer
2011HiPCImplementing a hybrid SRAM / eDRAM NUCA architecture.Javier Lira, Carlos Molina, David M. Brooks, Antonio Gonzlez
2011HPCAAchieving uniform performance and maximizing throughput in the presence of heterogeneity.Krishna K. Rangan, Michael D. Powell, Gu-Yeon Wei, David M. Brooks
2011IROSHardware in the loop for optical flow sensing in a robotic bee.Pierre-Emile Duhamel, Judson Porter, Benjamin M. Finio, Geoffrey L. Barrows, David M. Brooks, Gu-Yeon Wei, Robert J. Wood
2010MICROVoltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling.Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David M. Brooks
2009CASESAn accelerator-based wireless sensor network processor in 130nm CMOS.Mark Hempstead, Gu-Yeon Wei, David M. Brooks
2009DACSoftware-assisted hardware reliability: abstracting circuit-level challenges to the software stack.Vijay Janapa Reddi, Simone Campanoni, Meeta Sharma Gupta, Michael D. Smith, Gu-Yeon Wei, David M. Brooks
2009DATEAn event-guided approach to reducing voltage noise in processors.Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks
2009HPCAVoltage emergency prediction: Using signatures to reduce operating margins.Vijay Janapa Reddi, Meeta Sharma Gupta, Glenn H. Holloway, Gu-Yeon Wei, Michael D. Smith, David M. Brooks
2009ICCDDesign and test strategies for microarchitectural post-fabrication tuning.Xiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David M. Brooks
2009ICCDEmpirical performance models for 3T1D memories.Kristen Lovin, Benjamin C. Lee, Xiaoyao Liang, David M. Brooks, Gu-Yeon Wei
2009ISCAThread motion: fine-grained power management for multi-core systems.Krishna K. Rangan, Gu-Yeon Wei, David M. Brooks
2009ISLPEDThe design of a bloom filter hardware accelerator for ultra low power systems.Michael J. Lyons, David M. Brooks
2009MICROTribeca: design for PVT variations with local recovery and fine-grained adaptation.Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David M. Brooks
2008ASPLOSEfficiency trends and limits from comprehensive microarchitectural adaptivity.Benjamin C. Lee, David M. Brooks
2008HPCADeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors.Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David M. Brooks
2008HPCASystem level analysis of fast, per-core DVFS using on-chip switching regulators.Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, David M. Brooks
2008HPCARoughness of microarchitectural design topologies and its implications for optimization.Benjamin C. Lee, David M. Brooks
2008ICCADEvaluation of voltage interpolation to address process variations.Kevin Brownell, Gu-Yeon Wei, David M. Brooks
2008ISCAReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency.Xiaoyao Liang, Gu-Yeon Wei, David M. Brooks
2008ISCASSystem design considerations for sensor network applications.Mark Hempstead, Gu-Yeon Wei, David M. Brooks
2008ISLPEDInstruction-driven clock scheduling with glitch mitigation.Gu-Yeon Wei, David M. Brooks, Ali Durlov Khan, Xiaoyao Liang
2008MICROCPR: Composable performance regression for scalable multiprocessor models.Benjamin C. Lee, Jamison D. Collins, Hong Wang, David M. Brooks
2007DATEUnderstanding voltage variations in chip multiprocessors using a distributed power-delivery network.Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks
2007HPCAIllustrative Design Space Studies with Microarchitectural Regression Models.Benjamin C. Lee, David M. Brooks
2007ICCADArchitectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques.Xiaoyao Liang, Kerem Turgay, David M. Brooks
2007ISLPEDTowards a software approach to mitigate voltage emergencies.Meeta Sharma Gupta, Krishna K. Rangan, Michael D. Smith, Gu-Yeon Wei, David M. Brooks
2007MICROProcess Variation Tolerant 3T1D-Based Cache Architectures.Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David M. Brooks
2007PPoPPMethods of inference and learning for performance modeling of parallel applications.Benjamin C. Lee, David M. Brooks, Bronis R. de Supinski, Martin Schulz, Karan Singh, Sally A. McKee
2006ASPLOSAccurate and efficient regression modeling for microarchitectural performance and power prediction.Benjamin C. Lee, David M. Brooks
2006CASESArchitecture and circuit techniques for low-throughput, energy-constrained systems across technology generations.Mark Hempstead, Gu-Yeon Wei, David M. Brooks
2006CASESEfficient architectures through application clustering and architectural heterogeneity.Lukasz Strozek, David M. Brooks
2006HPCACMP design space exploration subject to physical constraints.Yingmin Li, Benjamin C. Lee, David M. Brooks, Zhigang Hu, Kevin Skadron
2006ICCADMicroarchitecture parameter selection to optimize system performance under process variation.Xiaoyao Liang, David M. Brooks
2006MICROMitigating the Impact of Process Variations on Processor Register Files and Execution Units.Xiaoyao Liang, David M. Brooks
2005HPCAPerformance, Energy, and Thermal Considerations for SMT and CMP Architectures.Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron
2005ISCAAn Ultra Low Power System Architecture for Sensor Network Applications.Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David M. Brooks
2005ISLPEDPower and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices.Yingmin Li, Mark Hempstead, Patrick Mauro, David M. Brooks, Zhigang Hu, Kevin Skadron
2005MICROA Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance.Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David M. Brooks
2004ICCDEvaluating Techniques for Exploiting Instruction Slack.Yau Chin, John Sheu, David M. Brooks
2004ISLPEDEliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization.Kim M. Hazelwood, David M. Brooks
2004ISLPEDUnderstanding the energy efficiency of simultaneous multithreading.Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
2004LCNTinyBench: The Case For A Standardized Benchmark Suite for TinyOS Based Wireless Sensor Network Devices.Mark Hempstead, Matt Welsh, David M. Brooks
2003HPCAControl Techniques to Eliminate Voltage Emergencies in High Performance Processors.Russ Joseph, David M. Brooks, Margaret Martonosi
2002MICROOptimizing pipelines for power and performance.Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma
2001HPCADynamic Thermal Management for High-Performance Microprocessors.David M. Brooks, Margaret Martonosi
2000ISCAWattch: a framework for architectural-level power analysis and optimizations.David M. Brooks, Vivek Tiwari, Margaret Martonosi
1999HPCADynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance.David M. Brooks, Margaret Martonosi