David M. Lewis

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

Venues

Active years

1985–2016

Best venue rank

Where they publish

Papers

27 indexed papers, newest first.

Year	Venue	Title	Authors
2016	FPGA	Stratix™ 10 High Performance Routable Clock Networks.	Carl Ebeling, Dana How, David M. Lewis, Herman Schmit
2016	FPGA	The Stratix™ 10 Highly Pipelined FPGA Architecture.	David M. Lewis, Gordon R. Chiu, Jeffrey Chromczak, David R. Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken
2013	FPGA	Architectural enhancements in Stratix V™.	David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu
2010	FPGA	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.	Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz
2009	FPGA	Architectural enhancements in Stratix-III	David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan
2005	FPGA	The Stratix II logic and routing architecture.	David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
2004	FPL	Improving FPGA Performance and Area Using an Adaptive Logic Module.	Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini
2003	FPGA	The Stratix	David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose
2002	FPGA	Circuit design of routing switches.	Guy G. Lemieux, David M. Lewis
2002	FPL	Analytical Framework for Switch Block Design.	Guy G. Lemieux, David M. Lewis
2001	FPGA	Using sparse crossbars within LUT.	Guy G. Lemieux, David M. Lewis
2000	FCCM	Design of a VLIW Compute Accelerator on the Transmogrifier-2.	L. Louis Zhang, Qiang Wang, David M. Lewis
2000	FPGA	Generating highly-routable sparse crossbars for PLDs.	Guy G. Lemieux, Paul Leventis, David M. Lewis
1999	FPGA	Procedural Texture Mapping on FPGAs.	Andy Gean Ye, David M. Lewis
1997	FCCM	Automated field-programmable compute accelerator design using partial evaluation.	Qiang Wang, David M. Lewis
1997	FPGA	The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System.	David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow
1996	FPGA	Area-Speed Tradeoffs for Hierarchical Field-Programmable Gate Arrays.	Vi Cuong Chan, David M. Lewis
1994	ICCD	Routing Architectures for Hierarchical Field Programmable Gate Arrays.	Aditya A. Aggarwal, David M. Lewis
1993	ARITH	An accurate LNS arithmetic unit using interleaved memory function interpolator.	David M. Lewis
1993	ICCD	A Field Programmable Accelerator for Compiled-Code Applications.	David M. Lewis, Marcus van Ierssel, Daniel H. Wong
1993	ISCAS	Highly Selective "Analog" Filters Using Delta Sigma Based IIR Filtering.	David A. Johns, David M. Lewis, Don Cherepacha
1990	ESORICS	Using Deducibility in Secure Network Modelling.	Brian W. Thomson, E. Stewart Lee, Peter I. P. Boulton, Michael Stumm, David M. Lewis
1989	ARITH	Algorithm design for a 30-bit integrated logarithmic processor.	David M. Lewis, Lawrence K. Yu
1989	ICCAD	Hierarchical compiled event-driven logic simulation.	David M. Lewis
1988	DAC	A Programmable Hardware Accelerator for Compiled Electrical Simulation.	David M. Lewis
1986	OOPSLA	Swamp: A Fast Processor for Smalltalk-80.	David M. Lewis, David R. Galloway, Robert J. Francis, Brian W. Thomson
1985	DAC	A hardware engine for analogue mode simulation of MOS digital circuits.	David M. Lewis