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David Walter

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

13

Venues

8

Active years

2003–2026

Best venue rank

A*

Where they publish

Papers

13 indexed papers, newest first.

YearVenueTitleAuthors
2026HCIExploring Informal Caregivers' Experiences with a Context-Sensitive Voice-Based AI Companion.David Walter, Paul-Ferdinand Steuck, Ralf Knackstedt
2025GISoftware Features of Informal Care Apps.David Walter, Thorsten Schoormann, Evelyn Emann, Ralf Knackstedt
2024GIFrom Hidden Care to Being Aware: Designing a Conversational Agent to Support Informal Caregivers in Seeking Assistance During Role Transition.David Walter, Paul-Ferdinand Steuck, Marco Di Maria, Ralf Knackstedt
2024GIModeling value exchange in informal care support ecosystems.David Walter, Kathrin Seibert, Marco Di Maria, Ralf Knackstedt
2023GIPromoting Sustainable Ecosystems through Interorganizational Unlearning - A Call for Research.Marco Di Maria, David Walter, Ralf Knackstedt
2018EMNLPSyntactical Analysis of the Weaknesses of Sentiment Analyzers.Rohil Verma, Samuel Kim, David Walter
2013SIGCSETeaching cyber-physical systems to computer scientists via modeling and verification.Kostadin Damevski, Badreldin Altayeb, Hui Chen, David Walter
2007ASPDACSymbolic Model Checking of Analog/Mixed-Signal Circuits.David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
2007ATVAAnalog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces.Scott Little, David Walter, Kevin R. Jones, Chris J. Myers
2007ATVABounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver.David Walter, Scott Little, Chris J. Myers
2006ICCADVerification of analog/mixed-signal circuits using labeled hybrid petri nets.Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda
2004ATVAVerification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets.Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
2003ICCDVerification of Timed Circuits with Failure Directed Abstractions.Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda