Davor Capalija
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
4
Active years
2006–2025
Best venue rank
B
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | HOTI | Panel: HotI 2025. | Peter Olcott, Phil Brown, Davor Capalija, Ethan Lockshin, Sid Sheth |
| 2018 | FPGA | In-Package Domain-Specific ASICs for Intel Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). | Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu |
| 2018 | FPL | In-Package Domain-Specific ASICs for Intel Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. | Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev |
| 2017 | FPGA | An OpenCL™ Deep Learning Accelerator on Arria 10. | Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu |
| 2014 | FPL | Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays. | Davor Capalija, Tarek S. Abdelrahman |
| 2013 | FPL | A high-performance overlay architecture for pipelined execution of data flow graphs. | Davor Capalija, Tarek S. Abdelrahman |
| 2011 | FCCM | Towards Synthesis-Free JIT Compilation to Commodity FPGAs. | Davor Capalija, Tarek S. Abdelrahman |
| 2006 | FCCM | A Multithreaded Soft Processor for SoPC Area Reduction. | Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown |