| 2024 | DSD | Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation. | Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das |
| 2024 | VLSID | Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs. | Tanusree Kaibartta, Hitarth Arora, Debesh Kumar Das |
| 2021 | VLSID | Minimization of Switching Activity of Graphene Based Circuits. | Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das |
| 2016 | DDECS | A rule-based approach for minimizing power dissipation of digital circuits. | Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das |
| 2016 | VLSID | Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. | Arindam Banerjee, Debesh Kumar Das |
| 2008 | VLSID | On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. | Hafizur Rahaman, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya |
| 2001 | VLSID | Testable Design of Sequential Circuits with Improved Fault Efficiency. | Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara |
| 2000 | ICCAD | Test Generation for Acyclic Sequential Circuits with Hold Registers. | Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara |
| 1997 | VLSID | New BIST Techniques for Universal and Robust Testing of CMOS Stuck-Open Faults. | Debesh Kumar Das, Susanta Chakraborty, Bhargab B. Bhattacharya |
| 1996 | VLSID | Does retiming affect redundancy in sequential circuits? | Debesh Kumar Das, Bhargab B. Bhattacharya |