| 2005 | ASPDAC | Supporting sequential assumptions in hybrid verification. | Eduard Cerny, Ashvin Dsouza, Kevin Harer, Pei-Hsin Ho, Hi-Keung Tony Ma |
| 2002 | ISCAS | Variable ordering on multiway decision graphs. | Yi Feng, Eduard Cerny |
| 2000 | FMCAD | Model Reductions and a Case Study. | Jin Hou, Eduard Cerny |
| 1999 | ICCD | Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. | Eduard Cerny, Fen Jin |
| 1999 | ISCAS | Synthesis of checker EFSMs from timing diagram specifications. | E. K. Ogoubi, Eduard Cerny |
| 1998 | CAV | Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs. | Ying Xu, Eduard Cerny, Xiaoyu Song, Francisco Corella, Otmane At Mohamed |
| 1998 | DATE | Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis. | Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel |
| 1998 | FMCAD | Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. | Fen Jin, Henrik Hulgaard, Eduard Cerny |
| 1997 | DATE | Interface timing verification with delay correlation using constraint logic programming. | Pierre Girodias, Eduard Cerny |
| 1997 | VTS | CLP-based Multifrequency Test Generation for Analog Circuits. | Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska |
| 1996 | CAV | MDG Tools for the Verification of RTL Designs. | K. D. Anon, N. Boulerice, Eduard Cerny, Francisco Corella, Michel Langevin, Xiaoyu Song, Sofine Tahar, Ying Xu, Zijian Zhou |
| 1996 | DATE | Bounding Switching Activity in CMOS Circuits Using Constraint Resolution. | Jindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin |
| 1996 | FMCAD | Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs. | Zijian Zhou, Xiaoyu Song, Sofine Tahar, Eduard Cerny, Francisco Corella, Michel Langevin |
| 1996 | ICCD | Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. | Michel Langevin, Sofine Tahar, Zijian Zhou, Xiaoyu Song, Eduard Cerny |
| 1995 | CP | Solving Linear, Min and Max Constraint Systems Using CLP based on Relational Interval Arithmetic. | Pierre Girodias, Eduard Cerny, William J. Older |
| 1994 | ISCAS | Modeling Cell Processing Hardware with Action Diagrams. | Karim Khordoc, Eduard Cerny |
| 1993 | ICCD | A Recursive Technique for Computing Lower-Bound Performance of Schedules. | Michel Langevin, Eduard Cerny |
| 1992 | ICCD | Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines. | Eduard Cerny |
| 1991 | CAV | Comparing Generic State Machines. | Michel Langevin, Eduard Cerny |
| 1991 | ICCAD | A Stimulus/Response System Based on Hierarchical Timing Diagrams. | Karim Khordoc, Mario Dufresne, Eduard Cerny |
| 1991 | ICCD | A Compositional Transformation for Formal Verification. | Eduard Cerny |
| 1990 | ICCAD | Tautology Checking Using Cross-Controllability and Cross-Observability Relations. | Eduard Cerny, C. Mauras |
| 1989 | ICCD | Magnitude classes in switch-level modeling. | Eduard Cerny, John P. Hayes, Nicholas C. Rumin |
| 1988 | ICCD | A class of fault-tolerant cellular permutation networks. | Mohsine Eleuldj, El Mostapha Aboulhamid, Eduard Cerny |
| 1987 | DAC | CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools. | Louis-Philippe Demers, P. Jacques, S. Fauvel, Eduard Cerny |
| 1985 | DAC | An object-oriented swicth-level simulator. | C. Roy, Louis-Philippe Demers, Eduard Cerny, Jan Gecsei |