Edward A. Stott
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
15
Venues
4
Active years
2008–2017
Best venue rank
A*
Where they publish
Papers
15 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | FPL | STRIPE: Signal selection for runtime power estimation. | James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | FCCM | KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. | Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | FPGA | Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). | James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2015 | FPGA | Delay-Bounded Routing for Shadow Registers. | Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk |
| 2014 | DAC | Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. | Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides |
| 2014 | FCCM | Timing Fault Detection in FPGA-Based Circuits. | Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre |
| 2014 | FPGA | Dynamic voltage & frequency scaling with online slack measurement. | Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung |
| 2013 | FPL | SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2012 | FCCM | Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2011 | FPGA | Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2011 | FPL | Improving FPGA Reliability with Wear-Levelling. | Edward A. Stott, Peter Y. K. Cheung |
| 2010 | FPGA | Degradation in FPGAs: measurement and modelling. | Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung |
| 2010 | FPL | Degradation Analysis and Mitigation in FPGAs. | Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung |
| 2009 | FPL | Compensating for variability in FPGAs by re-mapping and re-placement. | N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung |
| 2008 | FPL | Fault tolerant methods for reliability in FPGAs. | Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung |