| 2014 | ICS | Author retrospective for optimum modulo schedules for minimum register requirements. | Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham |
| 2008 | ICS | A freespace crossbar for multi-core processors. | Michel N. Victor, Aris K. Silzars, Edward S. Davidson |
| 2004 | CGO | Probabilistic Predicate-Aware Modulo Scheduling. | Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson |
| 2003 | CGO | Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints. | Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson, Hsien-Hsin S. Lee |
| 2002 | ICCD | TAXI: Trace Analysis for X86 Interpretation. | Stevan A. Vlaovic, Edward S. Davidson |
| 2002 | ICS | Boosting trace cache performance with nonhead miss speculation. | Stevan A. Vlaovic, Edward S. Davidson |
| 2001 | HPCA | Call Graph Prefetching for Database Applications. | Murali Annavaram, Jignesh M. Patel, Edward S. Davidson |
| 2001 | HPCA | Branch History Guided Instruction Prefetching. | Viji Srinivasan, Edward S. Davidson, Gary S. Tyson, Mark J. Charney, Thomas R. Puzak |
| 2001 | ICCD | Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. | Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson |
| 2001 | ISCA | Data prefetching by dependence graph precomputation. | Murali Annavaram, Jignesh M. Patel, Edward S. Davidson |
| 2000 | ISPASS | Instruction overhead and data locality effects in superscalar processors. | Murali Annavaram, Gary S. Tyson, Edward S. Davidson |
| 2000 | MICRO | Improving BTB performance in the presence of DLLs. | Stevan A. Vlaovic, Edward S. Davidson, Gary S. Tyson |
| 1999 | SODA | Dual-Issue Scheduling with Spills for Binary Trees. | Waleed Meleis, Edward S. Davidson |
| 1998 | ICCD | Evaluating the performance of active cache management schemes. | Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson |
| 1998 | ISCA | Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance. | Gheith A. Abandah, Edward S. Davidson |
| 1998 | ISCA | The Cedar System and an Initial Performance Study. | David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu |
| 1998 | ISCA | Improving the Throughput of a Pipeline by Insertion of Delays. | Janak H. Patel, Edward S. Davidson |
| 1998 | ISCA | Retrospective: The Cedar System. | Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle A. Gallivan |
| 1998 | ICS | Utilizing Reuse Information in Data Cache Management. | Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens |
| 1998 | MASCOTS | mlcache: A Flexible Multi-Lateral Cache Simulator. | Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson |
| 1997 | ICCD | On Effective Data Supply For Multi-Issue Processors. | Jude A. Rivers, Edward S. Tam, Edward S. Davidson |
| 1997 | MICRO | On High-Bandwidth Data Cache Design for Multi-Issue Processors. | Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin |
| 1997 | PLDI | Efficient Formulation for Optimal Modulo Schedulers. | Alexandre E. Eichenberger, Edward S. Davidson |
| 1996 | ICPP | Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. | Jude A. Rivers, Edward S. Davidson |
| 1996 | ICS | Profile Driven Weighted Decomposition. | Karen A. Tomko, Edward S. Davidson |
| 1996 | PLDI | A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints. | Alexandre E. Eichenberger, Edward S. Davidson |
| 1995 | ICCD | The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. | John-David Wellman, Edward S. Davidson |
| 1995 | ICS | Optimum Modulo Schedules for Minimum Register Requirements. | Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham |
| 1995 | MICRO | Register allocation for predicated code. | Alexandre E. Eichenberger, Edward S. Davidson |
| 1995 | MICRO | Stage scheduling: a technique to reduce the register requirements of a modulo schedule. | Alexandre E. Eichenberger, Edward S. Davidson |
| 1994 | ICPADS | Grouping Array Layouts to Reduce Communication and Improve Locality of Parallel Programs. | Tien-Pao Shih, Edward S. Davidson |
| 1994 | ICPP | A Hierarchical Approach to Modeling and Improving the Performance of Scientific Applications on the KSR1. | Eric L. Boyd, Waqar Azeem, Hsien-Hsin S. Lee, Tien-Pao Shih, Shih-Hao Hung, Edward S. Davidson |
| 1994 | ICS | Communication in the KSR1 MPP: performance evaluation using synthetic workload experiments. | Eric L. Boyd, Edward S. Davidson |
| 1994 | ICS | Optimal local register allocation for a multiple-issue machine. | Waleed Meleis, Edward S. Davidson |
| 1994 | MICRO | Minimum register requirements for a modulo schedule. | Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham |
| 1993 | ISCA | Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. | Eric L. Boyd, Edward S. Davidson |
| 1993 | ISCA | The Cedar System and an Initial Performance Study. | David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle A. Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, Ulrike Meier Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay P. Hoeflinger, Greg P. Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner |
| 1993 | ICS | Evaluating the Communication Performance of MPPs Using Synthetic Sparse Matrix Multiplication Workloads. | Eric L. Boyd, John-David Wellman, Santosh G. Abraham, Edward S. Davidson |
| 1992 | ICCAD | Using constraint geometry to determine maximum rate pipeline clocking. | Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah |
| 1992 | ICS | Register requirements of pipelined processors. | William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson |
| 1991 | ASPLOS | Vector Register Design for Polycyclic Vector Scheduling. | William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson |
| 1991 | ICCD | Optimal Clocking of Circular Pipelines. | Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson |
| 1991 | ICPP | The Organization of the Cedar System. | Jeff Konicek, Tracy Tilton, Alexander V. Veidenbaum, Chuan-Qi Zhu, Edward S. Davidson, Ruppert A. Downing, Michael J. Haney, Manish Sharma, Pen-Chung Yew, P. Michael Farmwald, David J. Kuck, Daniel M. Lavery, Robert A. Lindsey, D. Pointer, John T. Andrews, Thomas Beck, T. Murphy, Stephen W. Turner, Nancy J. Warter |
| 1991 | ICRA | An integrated approach to developing manufacturing control software. | Jarir K. Chaar, Richard A. Volz, Edward S. Davidson |
| 1990 | ICRA | Cyclic job shop scheduling using reservation tables. | Jarir K. Chaar, Edward S. Davidson |
| 1988 | ISCA | Analysis of Memory Referencing Behavior For Design of Local Memories. | Geoffrey D. McNiven, Edward S. Davidson |
| 1988 | ICS | An evaluation of Cray X-MP performance on vectorizable Livermore FORTRAN kernels. | J. H. Tang, Edward S. Davidson |
| 1988 | SC | Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers. | J. H. Tang, Edward S. Davidson, J. Tong |
| 1987 | ICPP | PSOLVE : A Concurrent Algorithm for Solving Sparse Systems of Linear Equations. | Timothy A. Davis, Edward S. Davidson |
| 1986 | ICPP | A Communication Model for Optimizing Hierarchical Multiprocessor Systems. | Santosh G. Abraham, Edward S. Davidson |
| 1986 | ISCA | Highly Concurrent Scalar Processing. | Peter Y.-T. Hsu, Edward S. Davidson |
| 1985 | ICASSP | A custom-designed integrated circuit for the realization of residue number digital filters. | W. K. Jenkins, Edward S. Davidson, D. F. Paul |
| 1985 | ISCA | TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. | Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham |
| 1985 | ISCA | An Efficient LISP-Execution Architecture with a New Representation for List Structures. | Gurindar S. Sohi, Edward S. Davidson, Janak H. Patel |
| 1984 | ISCA | Design of Instruction Set Architectures for Support of High-Level Languages . | Pradip Bose, Edward S. Davidson |
| 1983 | ICPP | Structured Memory Access Architecture. | Andrew R. Pleszkun, Edward S. Davidson |
| 1983 | ISCA | Performance of Shared Cache for Parallel-Pipelined Computer Systems | Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson |
| 1980 | ISCA | A Multiple Stream Microprocessor Prototype System: AMP-1. | Edward S. Davidson |
| 1977 | ISCA | Information Content of CPU Memory Referencing Behavior. | Dan W. Hammerstrom, Edward S. Davidson |
| 1976 | ISCA | Improving the Throughput of a Pipeline by Insertion of Delays. | Janak H. Patel, Edward S. Davidson |