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Engin Afacan

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

5

Active years

2014–2026

Best venue rank

C

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2026DDECSCo-Optimizing Performance and Security of Analog Integrated Circuits.Abdullah Bayram, Haralampos-G. Stratigopoulos, Engin Afacan
2026DDECSANN-Based Ultra Fast Synthesis of Flash ADCs.Abdullah Bayram, Hakan Taskiran, Engin Afacan
2022DATEReliability Analysis of a Spiking Neural Network Hardware Accelerator.Theofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuas-Mesa, Bernab Linares-Barranco, Haralampos-G. Stratigopoulos
2021DATENeuron Fault Tolerance in Spiking Neural Networks.Theofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuas-Mesa, Bernab Linares-Barranco, Haralampos-G. Stratigopoulos
2020IOLTSSpiking Neuron Hardware-Level Fault Modeling.Sarah A. El-Sayed, Theofilos Spyrou, Antonios Pavlidis, Engin Afacan, Luis A. Camuas-Mesa, Bernab Linares-Barranco, Haralampos-G. D. Stratigopoulos
2018DDECSA Rare Event Based Yield Estimation Methodology for Analog Circuits.Izel Cagin Odabasi, Mustafa Berke Yelten, Engin Afacan, I. Faik Baskaya, Ali Emre Pusane, Gnhan Dndar
2016DDECSA mixed domain sizing approach for RF circuit synthesis.Engin Afacan, Gnhan Dndar
2015DATEA hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool.Engin Afacan, Gnen Berkol, Ali Emre Pusane, Gnhan Dndar, I. Faik Baskaya
2015ISCASA novel yield aware multi-objective analog circuit optimization tool.Gnen Berkol, Engin Afacan, Gnhan Dndar, Ali Emre Pusane, I. Faik Baskaya
2014DATEModel based hierarchical optimization strategies for analog design automation.Engin Afacan, Simge Ay, Francisco V. Fernndez, Gnhan Dndar, I. Faik Baskaya
2014VTSReliability enhancement using in-field monitoring and recovery for RF circuits.Doohwang Chang, Sule Ozev, Bertan Bakkaloglu, Sayfe Kiaei, Engin Afacan, Gnhan Dndar