Eriko Nurvitadhi

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

Venues

Active years

2005–2026

Best venue rank

Where they publish

Papers

40 indexed papers, newest first.

Year	Venue	Title	Authors
2026	NSDI	FAST: An Efficient Scheduler for All-to-All GPU Communication.	Yiran Lei, Dongjoo Lee, Liangyu Zhao, Daniar Kurniawan, Chanmyeong Kim, Heetaek Jeong, Changsu Kim, Hyeonseong Choi, Liangcheng Yu, Arvind Krishnamurthy, Justine Sherry, Eriko Nurvitadhi
2022	FPL	RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices.	Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
2021	FCCM	Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs.	Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das
2021	FPGA	Stratix 10 NX Architecture and Applications.	Martin Langhammer, Eriko Nurvitadhi, Bogdan Pasca, Sergey Gribok
2021	FPL	End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression.	Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
2021	FPL	DO-GPU: Domain Optimizable Soft GPUs.	Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, Rajesh Vivekanandham, Aravind Dasu, Martin Langhammer, Derek Chiou
2020	DAC	Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels.	Dongup Kwon, Suyeon Hur, Hamin Jang, Eriko Nurvitadhi, Jangwoo Kim
2020	FCCM	Optimizing Reconfigurable Recurrent Neural Networks.	Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk
2020	FCCM	Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies.	Jessica Vandebon, Jos Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Tim Todman
2020	ICCAD	FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.	Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-Sun Seo
2019	FCCM	Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.	Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu
2019	FCCM	Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform.	Yu Wang, James C. Hoe, Eriko Nurvitadhi
2019	FPGA	Evaluating and Enhancing Intel Stratix 10 FPGAs for Persistent Real-Time AI.	Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu
2019	FPL	Specializing FGPU for Persistent Deep Learning.	Rui Ma, Derek Chiou, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu
2019	FPL	Automatic Compiler Based FPGA Accelerator for CNN Training.	Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
2018	FCCM	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs.	Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	FPGA	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs: (Abstract Only).	Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
2018	FPGA	A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.	Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
2018	FPGA	In-Package Domain-Specific ASICs for Intel Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
2018	FPL	In-Package Domain-Specific ASICs for Intel Stratix 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.	Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
2018	ICLR	WRPN: Wide Reduced-Precision Networks.	Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
2017	ASPDAC	Fine-grained accelerators for sparse machine learning workloads.	Asit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr
2017	FPGA	Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?	Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh
2017	FPL	High performance binary neural networks on the Xeon+FPGA™ platform.	Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
2017	ICASSP	Accelerating Deep Convolutional Networks using low-precision and sparsity.	Ganesh Venkatesh, Eriko Nurvitadhi, Debbie Marr
2016	DATE	Hardware accelerator for analytics of sparse data.	Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr
2016	FPGA	A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems.	Gabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe
2016	FPL	Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.	Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr
2015	CASES	A sparse matrix vector multiply accelerator for support vector machine.	Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr
2015	FPL	Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference.	Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, Jos F. Martnez, Rob A. Rutenbar
2014	ECCV	Programmable Automotive Headlights.	Robert Tamburo, Eriko Nurvitadhi, Abhishek Chugh, Mei Chen, Anthony Rowe, Takeo Kanade, Srinivasa G. Narasimhan
2014	FCCM	GraphGen: An FPGA Framework for Vertex-Centric Graph Computation.	Eriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, Jos F. Martnez, Carlos Guestrin
2013	CVPR	3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming.	Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen
2013	ICASSP	Hardware-efficient stereo estimation using a residual-based approach.	Abhishek A. Sharma, Kaustubh Neelathalli, Diana Marculescu, Eriko Nurvitadhi
2013	MEMOCODE	MEMOCODE 2013 hardware/software co-design contest: Stereo matching.	Eriko Nurvitadhi
2010	DAC	Automatic multithreaded pipeline synthesis from transactional datapath specifications.	Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam
2010	DATE	Automatic pipelining from transactional datapath specifications.	Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
2008	FPGA	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.	Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
2006	FPGA	Design, implementation, and verification of active cache emulator (ACE).	Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu
2005	ICS	Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C.	Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu