Eun Sei Park
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
1988–1998
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1998 | DAC | An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits. | Byunggyu Kwak, Eun Sei Park |
| 1995 | ISCAS | Automatic Synthesis of Gate-Level Speed-Independent Control Circuits from Signal Transition Graphs. | Sung Tae Jung, Eun Sei Park, Jung Sik Kim, Chu Shik Jhon |
| 1993 | ITC | Switch-Level ATPG Using Constraint-Guided Line Justification. | Eun Sei Park, M. Ray Mercer |
| 1991 | ITC | Delay Testing Quality in Timing-Optimized Designs. | Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer |
| 1990 | DAC | An Efficient Delay Test Generation System for Combinational Logic Circuits. | Eun Sei Park, M. Ray Mercer |
| 1988 | ITC | Statistical Delay Fault Coverage and Defect Level for Delay Faults. | Eun Sei Park, Thomas W. Williams, M. Ray Mercer |