| 2002 | DATE | CHESMIN: A Heuristic for State Reduction in Incompletely Specified Finite State Machines. | Sezer Gren, F. Joel Ferguson |
| 2002 | ITC | Testing Finite State Machines Based on a Structural Coverage Metric . | Sezer Gren, F. Joel Ferguson |
| 1999 | ITC | Checking sequence generation for asynchronous sequential elements. | Sezer Gren, F. Joel Ferguson |
| 1999 | VTS | Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test. | Michael A. Margolese, F. Joel Ferguson |
| 1999 | VTS | A Systematic DFT Procedure for Library Cells. | Jingjing Xu, Rahul Kundu, F. Joel Ferguson |
| 1998 | ITC | Cache RAM inductive fault analysis with fab defect modeling. | T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu |
| 1998 | ITC | On applying non-classical defect models to automated diagnosis. | Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess |
| 1998 | VTS | A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. | Douglas Williams, F. Joel Ferguson, Tracy Larrabee |
| 1997 | ITC | Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits. | Haluk Konuk, F. Joel Ferguson |
| 1997 | ITC | Bridging Fault Diagnosis in the Absence of Physical Information. | David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler |
| 1997 | ITC | Incorporating Physical Design-for-Test into Routing. | Richard McGowen, F. Joel Ferguson |
| 1997 | VTS | A methodolgy for characterizing cell testability. | Alvin Jee, F. Joel Ferguson |
| 1996 | VTS | An unexpected factor in testing for CMOS opens: the die surface. | Haluk Konuk, F. Joel Ferguson |
| 1995 | DAC | Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. | Haluk Konuk, F. Joel Ferguson, Tracy Larrabee |
| 1995 | ICCAD | Diagnosis of realistic bridging faults with single stuck-at information. | Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee |
| 1994 | ITC | Testing CMOS Logic Gates for Realistic Shorts. | Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee |
| 1994 | ITC | Defect Classes - An Overdue Paradigm for CMOS IC. | Charles F. Hawkins, Jerry M. Soden, Alan W. Righter, F. Joel Ferguson |
| 1994 | VTS | Eliminating undetectable shorts between horizontal wires during channel routing. | Richard McGowen, F. Joel Ferguson |
| 1993 | VTS | Physical design for testability for bridges in CMOS circuits. | F. Joel Ferguson |
| 1993 | VTS | Carafe: an inductive fault analysis tool for CMOS VLSI circuits. | Alvin Jee, F. Joel Ferguson |
| 1992 | VTS | On the effectiveness of simultaneous self-test techniques. | Peter A. Johnson, F. Joel Ferguson |
| 1991 | ITC | Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. | F. Joel Ferguson, Tracy Larrabee |
| 1991 | VTS | Test pattern generation for current testable faults in static CMOS circuits. | F. Joel Ferguson, Tracy Larrabee |
| 1990 | ITC | Testing for parametric faults in static CMOS circuits. | F. Joel Ferguson, Martin Taylor, Tracy Larrabee |
| 1988 | ITC | Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. | John Paul Shen, F. Joel Ferguson |
| 1984 | ITC | Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. | Wojciech Maly, F. Joel Ferguson, John Paul Shen |
| 1983 | ARITH | The design of two easily-testable VLSI array multipliers. | F. Joel Ferguson, John Paul Shen |