Fares Elsabbagh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
2020–2026
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCA | Lotus: A Multi-FPGA Task Dataflow Architecture to Accelerate Cycle-Level Simulation. | Fares Elsabbagh, Joel S. Emer, Daniel Snchez |
| 2023 | MICRO | Accelerating RTL Simulation with Hardware-Software Co-Design. | Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Snchez |
| 2021 | MICRO | Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics. | Blaise Tine, Krishna Praveen Yalamarthy, Fares Elsabbagh, Hyesoon Kim |
| 2020 | FPGA | Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping. | Blaise Tine, Fares Elsabbagh, Seyong Lee, Jeffrey S. Vetter, Hyesoon Kim |