| 2025 | ARITH | Hardware Fixed-Point 2D and 3D norms. | Romain Bouarah, Florent de Dinechin |
| 2025 | ARITH | Double-Word Decomposition in a Combined FP16, BF16 and FP32 Dot Product Add Operator. | Organe Desrentes, Benot Dupont de Dinechin, Florent de Dinechin |
| 2025 | DSD | Towards optimal reconfigurable constant multipliers. | Bastien Barbe, Xiao Peng, Anastasia Volkova, Florent de Dinechin |
| 2023 | ACSSC | Hardware-Optimal Digital FIR Filters: One ILP to Rule Them all and in Faithfulness Bind Them. | Anastasia Volkova, Rmi Garcia, Florent de Dinechin, Martin Kumm |
| 2023 | ARITH | Exact Fused Dot Product Add Operators. | Organe Desrentes, Benot Dupont de Dinechin, Florent de Dinechin |
| 2022 | FPL | Resource Optimal Squarers for FPGAs. | Andreas Bttcher, Martin Kumm, Florent de Dinechin |
| 2021 | ARITH | Resource Optimal Truncated Multipliers for FPGAs. | Andreas Bttcher, Martin Kumm, Florent de Dinechin |
| 2021 | ARITH | Towards Arithmetic-Centered Filter Design. | Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Anastasia Volkova |
| 2020 | DATE | Next Generation Arithmetic for Edge Computing. | Andre Guntoro, Cecilia De la Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar |
| 2019 | ARITH | Dynamic Precision Numerics Using a Variable-Precision UNUM Type I HW Coprocessor. | Andrea Bocco, Yves Durand, Florent de Dinechin |
| 2019 | ARITH | Reflections on 10 Years of FloPoCo. | Florent de Dinechin |
| 2019 | ARITH | Table-Based versus Shift-And-Add Constant Multipliers for FPGAs. | Florent de Dinechin, Silviu-Ioan Filip, Martin Kumm, Luc Forget |
| 2019 | FPL | Evaluating the Hardware Cost of the Posit Number System. | Yohann Uguen, Luc Forget, Florent de Dinechin |
| 2018 | ARITH | Karatsuba with Rectangular Multipliers for FPGAs. | Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, Peter Zipf |
| 2017 | DATE | Automating the pipeline of arithmetic datapaths. | Matei Istoan, Florent de Dinechin |
| 2017 | FCCM | A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. | Yohann Uguen, Florent de Dinechin, Steven Derrien |
| 2017 | FPL | Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. | Yohann Uguen, Florent de Dinechin, Steven Derrien |
| 2016 | ARITH | Computing floating-point logarithms with fixed-point operations. | Julien Le Maire, Nicolas Brunie, Florent de Dinechin, Jean-Michel Muller |
| 2015 | ARITH | Code Generators for Mathematical Functions. | Nicolas Brunie, Florent de Dinechin, Olga Kupriianova, Christoph Quirin Lauter |
| 2015 | ARITH | Hardware Implementations of Fixed-Point Atan2. | Florent de Dinechin, Matei Istoan |
| 2013 | FPL | Arithmetic core generation using bit heaps. | Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, Bogdan Popa |
| 2011 | ACSSC | A mixed-precision fused multiply and add. | Nicolas Brunie, Florent de Dinechin, Benot Dupont de Dinechin |
| 2011 | ARITH | The Arithmetic Operators You Will Never See in a Microprocessor. | Florent de Dinechin |
| 2010 | FPL | Multiplicative Square Root Algorithms for FPGAs. | Florent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy |
| 2010 | FPL | Pipelined FPGA Adders. | Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca |
| 2009 | FPL | Generating high-performance custom floating-point pipelines. | Florent de Dinechin, Cristian Klein, Bogdan Pasca |
| 2009 | FPL | Large multipliers with fewer DSP blocks. | Florent de Dinechin, Bogdan Pasca |
| 2008 | FPGA | When FPGAs are better at floating-point than microprocessors. | Florent de Dinechin, Jrmie Detrey, Octavian Cret, Radu Tudoran |
| 2007 | ARITH | Return of the hardware floating-point elementary function. | Jrmie Detrey, Florent de Dinechin, Xavier Pujol |
| 2007 | FPL | Floating-Point Trigonometric Functions for FPGAs. | Jrmie Detrey, Florent de Dinechin |
| 2006 | DSD | Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis. | Caroline Collange, Jrmie Detrey, Florent de Dinechin |
| 2006 | SAC | Assisted verification of elementary functions using Gappa. | Florent de Dinechin, Christoph Quirin Lauter, Guillaume Melquiond |
| 2005 | ARITH | Towards the Post-Ultimate libm. | Florent de Dinechin, Alexey V. Ershov, Nicolas Gast |
| 2004 | FPL | Second Order Function Approximation Using a Single Multiplication on FPGAs. | Jrmie Detrey, Florent de Dinechin |
| 2003 | PACT | Software Carry-Save: A Case Study for Instruction-Level Parallelism. | David Defour, Florent de Dinechin |
| 2001 | ARITH | Some Improvements on Multipartite Table Methods . | Florent de Dinechin, Arnaud Tisserand |
| 2000 | PDPTA | Constant Multipliers for FPGAs. | Florent de Dinechin, Vincent Lefvre |
| 1999 | FPGA | Towards Adaptable Hierarchical Placement for FPGAs. | Florent de Dinechin, Wayne Luk, Steve McKeever |