| 2026 | DATE | Entropy Sampling-Based Neural Architecture Search for Resource-Constrained Microcontroller Targets. | Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jrgen Teich |
| 2026 | DATE | Multi-Partner Project: A Holistic and Open-Source Approach to Efficient, Secure and Reliable AI Hardware Deployment in DI-EDAI. | Georgios Sotiropoulos, Felix Frombach, Julian Hfer, Tanja Harbaum, Jrgen Becker, Henrik Iver Thore, Vincent Meyers, Mehdi B. Tahoori, Zeynep Demirdag, Mohammed Bakr Sikal, Hassan Nassar, Heba Khdr, Jrg Henkel, Christopher Wolters, Philipp van Kempen, Johannes Geier, Ulf Schlichtmann, Batuhan Sesli, Muhammad Sabih, Jakob Wittmann, Frank Hannig, Jrgen Teich, Lukas Steiner, Norbert Wehn, Mohamed Shelkamy Ali, Philipp Schmitz, Wolfgang Kunz, Stefan Koegler, Georg Sigl |
| 2025 | ICCAD | Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow. | Batuhan Sesli, Muhammad Sabih, Frank Hannig, Jrgen Teich |
| 2024 | DATE | Accelerating DNNs Using Weight Clustering on RISC-V Custom Functional Units. | Muhammad Sabih, Batuhan Sesli, Frank Hannig, Jrgen Teich |
| 2024 | DSD | DSL-Based SNN Accelerator Design Using Chisel. | Patrick Plagwitz, Frank Hannig, Jrgen Teich, Oliver Keszcze |
| 2024 | ISCAS | ALPACA: An Accelerator Chip for Nested Loop Programs. | Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2024 | VEHITS | Efficient Deployment of Neural Networks for Thermal Monitoring on AURIX TC3xx Microcontrollers. | Christian Heidorn, Frank Hannig, Dominik Riedelbauch, Christoph Strohmeyer, Jrgen Teich |
| 2023 | EuroSys | Robust and Tiny Binary Neural Networks using Gradient-based Explainability Methods. | Muhammad Sabih, Mikail Yayla, Frank Hannig, Jrgen Teich, Jian-Jia Chen |
| 2022 | EuroSys | DyFiP: explainable AI-based dynamic filter pruning of convolutional neural networks. | Muhammad Sabih, Frank Hannig, Jrgen Teich |
| 2022 | FPL | TRAC: Compilation-Based Design of Transformer Accelerators for FPGAs. | Patrick Plagwitz, Frank Hannig, Jrgen Teich |
| 2021 | DSN | Fault-Tolerant Low-Precision DNNs using Explainable AI. | Muhammad Sabih, Frank Hannig, Jrgen Teich |
| 2021 | FCCM | A Safari through FPGA-based Neural Network Compilation and Design Automation Flows. | Patrick Plagwitz, Frank Hannig, Martin Strbel, Christoph Strohmeyer, Jrgen Teich |
| 2021 | FPL | Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays. | Christian Heidorn, Dominik Walter, Yunus Emre Candir, Frank Hannig, Jrgen Teich |
| 2021 | SCOPES | Efficient Application of Tensor Core Units for Convolving Images. | Stefan Groth, Jrgen Teich, Frank Hannig |
| 2020 | DAC | The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. | Bo Qiao, M. Akif zkan, Jrgen Teich, Frank Hannig |
| 2020 | EuroPar | HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids. | Samer Alhaddad, Jens Frstner, Stefan Groth, Daniel Grnewald, Yevgen Grynko, Frank Hannig, Tobias Kenter, Franz-Josef Pfreundt, Christian Plessl, Merlind Schotte, Thomas Steinke, Jrgen Teich, Martin Weiser, Florian Wende |
| 2020 | PPoPP | Unveiling kernel concurrency in multiresolution filters on GPUs with an image processing DSL. | Bo Qiao, Oliver Reiche, Jrgen Teich, Frank Hannig |
| 2020 | SCOPES | Design space exploration for layer-parallel execution of convolutional neural networks on CGRAs. | Christian Heidorn, Frank Hannig, Jrgen Teich |
| 2020 | SCOPES | Efficient parallel reduction on GPUs with Hipacc. | Bo Qiao, Oliver Reiche, M. Akif zkan, Jrgen Teich, Frank Hannig |
| 2019 | CGO | From Loop Fusion to Kernel Fusion: A Domain-Specific Approach to Locality Optimization. | Bo Qiao, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2019 | MEMOCODE | Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays. | Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2019 | SCOPES | SYCL Code Generation for Multigrid Methods. | Stefan Groth, Christian Schmitt, Jrgen Teich, Frank Hannig |
| 2018 | DATE | Cell-based update algorithm for occupancy grid maps and hybrid map for ADAS on embedded GPUs. | Jrg Fickenscher, Jens Schlumberger, Frank Hannig, Jrgen Teich, Mohamed Essayed Bouzouraa |
| 2018 | FCCM | OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. | Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Frstner, Christian Plessl |
| 2018 | SCOPES | Automatic Kernel Fusion for Image Processing DSLs. | Bo Qiao, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2018 | VEHITS | Base Algorithms of Environment Maps and Efficient Occupancy Grid Mapping on Embedded GPUs. | Jrg Fickenscher, Frank Hannig, Jrgen Teich, Mohamed Essayed Bouzouraa |
| 2017 | ICCAD | Generating FPGA-based image processing accelerators with Hipacc: (Invited paper). | Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jrgen Teich, Frank Hannig |
| 2017 | RSP | Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates. | Michael Witterauf, Frank Hannig, Jrgen Teich |
| 2016 | FPL | FPGA-based accelerator design from a domain-specific language. | M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2016 | PLDI | ActorX10: an actor library for X10. | Sascha Roloff, Alexander Pppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Gla, Frank Hannig, Jrgen Teich |
| 2015 | DAC | Execution-driven parallel simulation of PGAS applications on heterogeneous tiled architectures. | Sascha Roloff, David Schafhauser, Frank Hannig, Jrgen Teich |
| 2015 | MEMOCODE | Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays. | Alexandru Tanase, Michael Witterauf, Jrgen Teich, Frank Hannig |
| 2015 | SCOPES | Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. | ricles Sousa, Frank Hannig, Jrgen Teich, Qingqing Chen, Ulf Schlichtmann |
| 2014 | ACSSC | Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. | Deepak Gangadharan, ricles Sousa, Vahid Lari, Frank Hannig, Jrgen Teich |
| 2014 | DATE | Code generation for embedded heterogeneous architectures on android. | Richard Membarth, Oliver Reiche, Frank Hannig, Jrgen Teich |
| 2014 | DSD | Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. | ricles Sousa, Deepak Gangadharan, Frank Hannig, Jrgen Teich |
| 2014 | EuroPar | ExaStencils: Advanced Stencil-Code Engineering. | Christian Lengauer, Sven Apel, Matthias Bolten, Armin Grlinger, Frank Hannig, Harald Kstler, Ulrich Rde, Jrgen Teich, Alexander Grebhahn, Stefan Kronawitter, Sebastian Kuckuk, Hannah Rittich, Christian Schmitt |
| 2014 | FPL | An image processing library for C-based high-level synthesis. | Moritz Schmid, Nicolas Apelt, Frank Hannig, Jrgen Teich |
| 2014 | ICCSA | An Evaluation of Domain-Specific Language Technologies for Code Generation. | Christian Schmitt, Sebastian Kuckuk, Harald Kstler, Frank Hannig, Jrgen Teich |
| 2014 | MEMOCODE | Symbolic inner loop parallelisation for massively parallel processor arrays. | Alexandru Tanase, Michael Witterauf, Jrgen Teich, Frank Hannig |
| 2014 | SC | ExaSlang: a domain-specific language for highly scalable multigrid solvers. | Christian Schmitt, Sebastian Kuckuk, Frank Hannig, Harald Kstler, Jrgen Teich |
| 2013 | SCOPES | NoC simulation in heterogeneous architectures for PGAS programming model. | Sascha Roloff, Andreas Weichslgartner, Jan Heiwolf, Frank Hannig, Jrgen Teich |
| 2012 | ASPDAC | Approximate time functional simulation of resource-aware programming concepts for heterogeneous MPSoCs. | Sascha Roloff, Frank Hannig, Jrgen Teich |
| 2012 | EuroPar | Mastering Software Variant Explosion for GPU Accelerators. | Richard Membarth, Frank Hannig, Jrgen Teich, Mario Krner, Wieland Eckert |
| 2012 | FCCM | Power Management Strategies for Serial RapidIO Endpoints in FPGAs. | Moritz Schmid, Frank Hannig, Jrgen Teich |
| 2012 | FDL | An integrated simulation framework for invasive computing. | Michael Gerndt, Frank Hannig, Andreas Herkersdorf, Andreas Hollmann, Marcel Meyer, Sascha Roloff, Josef Weidendorfer, Thomas Wild, Aurang Zaib |
| 2012 | ISPDC | Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators Based on a Domain-Specific Language for Medical Imaging. | Richard Membarth, Frank Hannig, Jrgen Teich, Mario Krner, Wieland Eckert |
| 2012 | SC | Towards Domain-Specific Computing for Stencil Codes in HPC. | Richard Membarth, Frank Hannig, Jrgen Teich, Harald Kstler |
| 2012 | SCOPES | Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation. | Sascha Roloff, Frank Hannig, Jrgen Teich |
| 2011 | SCOPES | Resource-aware programming and simulation of MPSoC architectures through extension of X10. | Frank Hannig, Sascha Roloff, Gregor Snelting, Jrgen Teich, Andreas Zwinkau |
| 2009 | DATE | Model-based synthesis and optimization of static multi-rate image processing algorithms. | Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jrgen Teich |
| 2008 | DSD | Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. | Rainer Schaffer, Renate Merker, Frank Hannig, Jrgen Teich |
| 2008 | DSD | Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. | Christophe Wolinski, Krzysztof Kuchcinski, Jrgen Teich, Frank Hannig |
| 2008 | FCCM | Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. | Christophe Wolinski, Krzysztof Kuchcinski, Jrgen Teich, Frank Hannig |
| 2008 | FPL | Coarse-grained reconfiguration. | Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jrgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jrgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner |
| 2008 | FPL | Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. | Christophe Wolinski, Krzysztof Kuchcinski, Jrgen Teich, Frank Hannig |
| 2007 | SCOPES | Efficient event-driven simulation of parallel processor architectures. | Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jrgen Teich |
| 2004 | ICASSP | Regular mapping for coarse-grained reconfigurable architectures. | Frank Hannig, Hritam Dutta, Jrgen Teich |
| 2002 | SPAA | Energy estimation of nested loop programs. | Frank Hannig, Jrgen Teich |
| 2001 | PACT | Design Space Exploration for Massively Parallel Processor Arrays. | Frank Hannig, Jrgen Teich |