Frank K. Grkaynak
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
28
Venues
13
Active years
1999–2023
Best venue rank
A*
Where they publish
Papers
28 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2023 | DATE | PetaOps/W edge-AI $\mu$ Processors: Myth or reality? | Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Grkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Gneysu, Henk Corporaal |
| 2023 | ISCAS | Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. | MohammadHossein AskariHemmat, Tho Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Grkaynak, Luca Benini, Franois Leduc-Primeau, Yvon Savaria, Jean-Pierre David |
| 2021 | DATE | Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. | Nils Wistoff, Moritz Schneider, Frank K. Grkaynak, Luca Benini, Gernot Heiser |
| 2021 | ETS | Security, Reliability and Test Aspects of the RISC-V Ecosystem. | Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Grkaynak, Helena Handschuh, Carles Hernndez, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni |
| 2020 | DSD | The ECSEL FRACTAL Project: A Cognitive Fractal and Secure edge based on a unique Open-Safe-Reliable-Low Power Hardware Platform. | Aizea Lojo, Leire Rubio, Jesus Miguel Ruano, Tania Di Mascio, Luigi Pomante, Enrico Ferrari, Ignacio Garca Vega, Frank K. Grkaynak, Mikel Labayen Esnaola, Vanessa Orani, Jaume Abella |
| 2018 | DATE | High speed ASIC implementations of leakage-resilient cryptography. | Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Grkaynak, Michael Muehlberghuber, Luca Benini |
| 2018 | ISCAS | An 826 MOPS, 210uW/MHz Unum ALU in 65 nm. | Florian Glaser, Stefan Mach, Abbas Rahimi, Frank K. Grkaynak, Qiuting Huang, Luca Benini |
| 2017 | CARDIS | Leakage Bounds for Gaussian Side Channels. | Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank K. Grkaynak, Michael Muehlberghuber |
| 2016 | ARITH | Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters. | Michael Schaffner, Michael Gautschi, Frank K. Grkaynak, Luca Benini |
| 2016 | DATE | High-efficiency logarithmic number unit design based on an improved cotransformation scheme. | Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank K. Grkaynak, Luca Benini |
| 2015 | DATE | DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. | Michael Schaffner, Frank K. Grkaynak, Aljoscha Smolic, Luca Benini |
| 2015 | VCIP | Automatic multiview synthesis - Towards a mobile system on a chip. | Michael Schaffner, Frank K. Grkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic |
| 2015 | VCIP | Automatic multiview synthesis - Prototype demo. | Michael Schaffner, Frank K. Grkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic |
| 2014 | DAC | An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. | Michael Schaffner, Frank K. Grkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini |
| 2014 | ISCAS | Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. | Christoph Keller, Frank K. Grkaynak, Hubert Kaeslin, Norbert Felber |
| 2013 | ISCA | Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC. | Michael Muehlberghuber, Frank K. Grkaynak, Thomas Korak, Philipp Dunst, Michael Hutter |
| 2010 | CHES | Developing a Hardware Evaluation Method for SHA-3 Candidates. | Luca Henzen, Pietro Gendotti, Patrice Guillet, Enrico Pargaetzi, Martin Zoller, Frank K. Grkaynak |
| 2008 | CASES | Design space exploration for field programmable compressor trees. | Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | DATE | A Generic Standard Cell Design Methodology for Differential Circuit Styles. | Stphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Grkaynak, Yusuf Leblebici |
| 2008 | DATE | Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. | Carlotta Guiducci, Alexandre Schmid, Frank K. Grkaynak, Yusuf Leblebici |
| 2008 | FPGA | Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | ISCAS | Improving the power-delay product in SCL circuits using source follower output stage. | Armin Tajalli, Frank K. Grkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer |
| 2003 | ISCAS | Variable delay ripple carry adder with carry chain interrupt detection. | Andreas Burg, Frank K. Grkaynak, Hubert Kaeslin, Wolfgang Fichtner |
| 2002 | CHES | 2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. | Adrian K. Lutz, Jrg Treichler, Frank K. Grkaynak, Hubert Kaeslin, Grard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner |
| 2000 | ICASSP | A compact modular architecture for high-speed binary sorting. | Ilhan Hatirnaz, Frank K. Grkaynak, Yusuf Leblebici |
| 2000 | ISCAS | Higher radix Kogge-Stone parallel prefix adder architectures. | Frank K. Grkaynak, Yusuf Leblebici, Laurent Chaouat, Patrik J. McGuinness |
| 2000 | ISCAS | A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. | Ilhan Hatirnaz, Frank K. Grkaynak, Yusuf Leblebici |
| 1999 | ISCAS | Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. | Ilhan Hatirnaz, Frank K. Grkaynak, Yusuf Leblebici |