Gabriel H. Loh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
73
Venues
19
Active years
1999–2025
Best venue rank
A*
Where they publish
Papers
73 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPLOS | Load and MLP-Aware Thread Orchestration for Recommendation Systems Inference on CPUs. | Rishabh Jain, Teyuh Chou, Onur Kayiran, John Kalamatianos, Gabriel H. Loh, Mahmut T. Kandemir, Chita R. Das |
| 2024 | ISCA | Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. | Alan Smith, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, Nathan Kalyanasundharam, Vamsi Alla, Nicholas Malaya, Joseph L. Greathouse, Eric Chapman, Raja Swaminathan |
| 2023 | DATE | The Next Era for Chiplet Innovation. | Gabriel H. Loh, Raja Swaminathan |
| 2023 | ISCA | A Research Retrospective on AMD's Exascale Computing Journey. | Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, Johnathan Alsop, Paul T. Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William C. Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliot Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Gregory Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, Ren van Oostrum, Eric Van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov |
| 2021 | DATE | Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. | Gabriel H. Loh, Samuel Naffziger, Kevin Lepak |
| 2021 | HPCA | Analyzing and Leveraging Decoupled L1 Caches in GPUs. | Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh, Adwait Jog |
| 2021 | ISCA | Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product. | Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, Sean White |
| 2021 | MICRO | Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources. | Jagadish B. Kotra, Michael LeBeane, Mahmut T. Kandemir, Gabriel H. Loh |
| 2020 | HPCA | Experiences with ML-Driven Design: A NoC Case Study. | Jieming Yin, Subhash Sethumurugan, Yasuko Eckert, Chintan Patel, Alan Smith, Eric Morton, Mark Oskin, Natalie D. Enright Jerger, Gabriel H. Loh |
| 2019 | DAC | Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory. | Dylan C. Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Xueqi Li, Gabriel H. Loh |
| 2018 | ICCAD | Machine learning for performance and power modeling of heterogeneous systems. | Joseph L. Greathouse, Gabriel H. Loh |
| 2018 | ISCA | Scheduling Page Table Walks for Irregular GPU Applications. | Seunghee Shin, Guilherme Cox, Mark Oskin, Gabriel H. Loh, Yan Solihin, Abhishek Bhattacharjee, Arkaprava Basu |
| 2018 | ISCA | Generic System Calls for GPUs. | Jn Vesel, Arkaprava Basu, Abhishek Bhattacharjee, Gabriel H. Loh, Mark Oskin, Steven K. Reinhardt |
| 2018 | ISCA | Modular Routing Design for Chiplet-Based Systems. | Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natalie D. Enright Jerger, Gabriel H. Loh |
| 2018 | SC | Challenges of High-Capacity DRAM Stacks and Potential Directions. | Amin Farmahini Farahani, Sudhanva Gurumurthi, Gabriel H. Loh, Michael Ignatowski |
| 2017 | HPCA | MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories. | Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen |
| 2017 | HPCA | Design and Analysis of an APU for Exascale Computing. | Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan |
| 2017 | ICCAD | Cost-effective design of scalable high-performance systems using active and passive interposers. | Dylan C. Stow, Yuan Xie, Taniya Siddiqua, Gabriel H. Loh |
| 2017 | ISCA | There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. | Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh |
| 2017 | SC | Leveraging near data processing for high-performance checkpoint/restart. | Abhinav Agrawal, Gabriel H. Loh, James Tuck |
| 2016 | HPCA | Efficient synthetic traffic models for large, complex SoCs. | Jieming Yin, Onur Kayiran, Matthew Poremba, Natalie D. Enright Jerger, Gabriel H. Loh |
| 2016 | ISPASS | Observations and opportunities in architecting shared virtual memory for heterogeneous systems. | Jn Vesel, Arkaprava Basu, Mark Oskin, Gabriel H. Loh, Abhishek Bhattacharjee |
| 2016 | MICRO | OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures. | Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie |
| 2016 | SBAC-PAD | Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. | Zhe Wang, Daniel A. Jimnez, Tao Zhang, Gabriel H. Loh, Yuan Xie |
| 2015 | HPCA | Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories. | Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh |
| 2015 | MICRO | Enabling interposer-based disintegration of multi-core processors. | Ajaykumar Kannan, Natalie D. Enright Jerger, Gabriel H. Loh |
| 2015 | MICRO | Large pages and lightweight memory management in virtualized environments: can you have it both ways? | Binh Pham, Jn Vesel, Gabriel H. Loh, Abhishek Bhattacharjee |
| 2014 | HPCA | Increasing TLB reach by exploiting clustering in page translations. | Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, Gabriel H. Loh |
| 2014 | ICS | Last-level cache deduplication. | Yingying Tian, Samira Manabi Khan, Daniel A. Jimnez, Gabriel H. Loh |
| 2014 | ITC | Efficient RAS support for die-stacked DRAM. | Hyeran Jeon, Gabriel H. Loh, Murali Annavaram |
| 2014 | MICRO | NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free? | Natalie D. Enright Jerger, Ajaykumar Kannan, Zimo Li, Gabriel H. Loh |
| 2014 | MICRO | Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache. | Djordje Jevdjic, Gabriel H. Loh, Cansu Kaynak, Babak Falsafi |
| 2014 | MICRO | Managing GPU Concurrency in Heterogeneous Architectures. | Onur Kayiran, Nachiappan Chidambaram Nachiappan, Adwait Jog, Rachata Ausavarungnirun, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das |
| 2014 | SC | Managing DRAM Latency Divergence in Irregular GPGPU Applications. | Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian |
| 2014 | SC | Toward efficient programmer-managed two-level memory hierarchies in exascale computers. | Mitesh R. Meswani, Gabriel H. Loh, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski |
| 2014 | SBAC-PAD | Design and Evaluation of Hierarchical Rings with Deflection Routing. | Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu |
| 2013 | ISCA | Resilient die-stacked DRAM caches. | Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor |
| 2012 | ISCA | Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. | Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu |
| 2012 | ISLPED | Energy-efficient GPU design with reconfigurable in-package graphics memory. | Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie |
| 2012 | MICRO | Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design. | Moinuddin K. Qureshi, Gabriel H. Loh |
| 2012 | MICRO | A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. | Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi |
| 2011 | ICCD | Thread-aware dynamic shared cache compression in multi-core processors. | Yuejian Xie, Gabriel H. Loh |
| 2011 | MICRO | Preventing PCM banks from seizing too much power. | Andrew W. Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger |
| 2011 | MICRO | A register-file approach for row buffer caches in die-stacked DRAMs. | Gabriel H. Loh |
| 2011 | MICRO | Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. | Gabriel H. Loh, Mark D. Hill |
| 2010 | DAC | Quantifying and coping with parametric variations in 3D-stacked microarchitectures. | Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel H. Loh, Alok N. Choudhary |
| 2010 | ISCA | Use ECP, not ECC, for hard failures in resistive memories. | Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger |
| 2009 | ASPDAC | Thermal optimization in multi-granularity multi-core floorplanning. | Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim |
| 2009 | HPCA | Criticality-based optimizations for efficient load processing. | Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh |
| 2009 | ISCA | PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. | Yuejian Xie, Gabriel H. Loh |
| 2009 | ISPASS | Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. | Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie |
| 2009 | MICRO | Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. | Gabriel H. Loh |
| 2008 | HPCA | PEEP: Exploiting predictability of memory dependences in SMT processors. | Samantika Subramaniam, Milos Prvulovic, Gabriel H. Loh |
| 2008 | ISCA | 3D-Stacked Memory Architectures for Multi-core Processors. | Gabriel H. Loh |
| 2008 | SBAC-PAD | A Segmented Bloom Filter Algorithm for Efficient Predictors. | Maurcio Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeff Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu |
| 2007 | DAC | Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. | Kiran Puttaswamy, Gabriel H. Loh |
| 2007 | HPCA | Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. | Kiran Puttaswamy, Gabriel H. Loh |
| 2007 | ISCA | Matrix scheduler reloaded. | Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black |
| 2006 | CASES | Entropy-based low power data TLB design. | Chinnakrishnan S. Ballapuram, Kiran Puttaswamy, Gabriel H. Loh, Hsien-Hsin S. Lee |
| 2006 | DATE | Microarchitectural floorplanning under performance and thermal tradeoff. | Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh |
| 2006 | HPCA | Store vectors for scalable memory dependence prediction and scheduling. | Samantika Subramaniam, Gabriel H. Loh |
| 2006 | ISCAS | The impact of 3-dimensional integration on the design of arithmetic units. | Kiran Puttaswamy, Gabriel H. Loh |
| 2006 | ISPASS | Revisiting the performance impact of branch predictor latencies. | Gabriel H. Loh |
| 2006 | MICRO | Die Stacking (3D) Microarchitecture. | Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb |
| 2006 | MICRO | Fire-and-Forget: Load/Store Scheduling with No Store Queue at All. | Samantika Subramaniam, Gabriel H. Loh |
| 2006 | MICRO | Adaptive Caches: Effective Shaping of Cache Behavior to Workloads. | Ranjith Subramanian, Yannis Smaragdakis, Gabriel H. Loh |
| 2006 | SBAC-PAD | Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. | Daniel A. Jimnez, Gabriel H. Loh |
| 2005 | ICCD | Implementing Caches in a 3D Technology for High Performance Processors. | Kiran Puttaswamy, Gabriel H. Loh |
| 2005 | ISPASS | Simulation Differences Between Academia and Industry: A Branch Prediction Case Study. | Gabriel H. Loh |
| 2002 | MICRO | Exploiting data-width locality to increase superscalar execution bandwidth. | Gabriel H. Loh |
| 2001 | SIGMETRICS | A time-stamping algorithm for efficient performance estimation of superscalar processors. | Gabriel H. Loh |
| 2000 | ISCA | Circuits for wide-window superscalar processors. | Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh, Rahul Sami |
| 1999 | SPAA | A Comparison of Scalable Superscalar Processors. | Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh |