Giacinto Paolo Saggese
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
5
Active years
2002–2006
Best venue rank
Unranked
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | EDCC | Dynamic Derivation of Application-Specific Error Detectors and their Implementation in Hardware. | Karthik Pattabiraman, Giacinto Paolo Saggese, Daniel Chen, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
| 2005 | DSN | Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic. | Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
| 2005 | EDCC | An Architectural Framework for Detecting Process Hangs/Crashes. | Nithin Nakka, Giacinto Paolo Saggese, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
| 2004 | DATE | Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware. | Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese |
| 2004 | SRDS | Hardware Support for High Performance, Intrusion- and Fault-Tolerant Systems. | Giacinto Paolo Saggese, Claudio Basile, Luigi Romano, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
| 2003 | DATE | FPGA-Based Implementation of a Serial RSA Processor. | Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Nicola Mazzocca |
| 2003 | FPL | An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm. | Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo |
| 2002 | FPL | A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations. | Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo |