Gian Carlo Cardarilli
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
52
Venues
4
Active years
1988–2026
Best venue rank
C
Where they publish
Papers
52 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | Low-Complexity and Resource-Efficient Design of a Streaming Channel Estimation for ZP-OTFS. | Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Riccardo La Cesa, Marco Re, Sergio Span, Cristian Valenti |
| 2025 | ACSSC | Exploring the Limits of High-Throughput Wideband Digital Signal Processing on AMD Versal AI Engines and Programmable Logic: Insights from a Polyphase Filter Bank Deployment. | Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Riccardo La Cesa, Marco Re, Sergio Span, Cristian Valenti |
| 2024 | ACSSC | A RISC-V Hardware Accelerator for AW-SOM Machine Learning. | Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Riccardo La Cesa, Mariano Neroni, Simone Pace, Sergio Span |
| 2023 | ACSSC | A Hardware-Oriented QAM Demodulation Method Driven by AW-SOM Machine Learning. | Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Span |
| 2023 | ACSSC | Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Alberto Nannarelli, Marco Re |
| 2021 | ACSSC | "MR Q-Learning" Algorithm for Efficient Hardware Implementations. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Dario Natale, Marco Re, Sergio Span |
| 2020 | ACSSC | FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re, Sergio Span |
| 2019 | ACSSC | Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re |
| 2018 | ACSSC | A Power Efficient Digital Front-End for Cognitive Radio Systems. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re |
| 2017 | ISCAS | A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Luca Gerardi, Marco Re, Giovanni Campolo, Domenico Cascone |
| 2016 | ACSSC | Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. | A. Esposito, Andrea Lomuscio, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re |
| 2013 | ACSSC | Truncated multipliers through power-gating for degrading precision arithmetic. | Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re |
| 2013 | ACSSC | Spiking neural networks based on LIF with latency: Simulation and synchronization effects. | Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Marco Re, Mario Salerno, Gianluca Susi |
| 2013 | ACSSC | Compressive sensing spectrum analysis for space autonomous radio receivers. | Gian Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone |
| 2012 | ACSSC | Imprecise arithmetic for low power image processing. | Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re |
| 2012 | ACSSC | Karatsuba implementation of FIR filters. | Pietro Albicocco, Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re |
| 2012 | ACSSC | Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Ruby B. Lee |
| 2012 | ACSSC | Power efficient design of parallel/serial FIR filters in RNS. | Massimo Petricca, Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re |
| 2011 | ACSSC | Fine-grain Reconfigurable Functional Unit for embedded processors. | Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re |
| 2009 | IOLTS | Error detection in addition chain based ECC Point Multiplication. | Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano |
| 2009 | ISCAS | Arithmetic/Logic Blocks for Fine-grained Reconfigurable Units. | Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re |
| 2009 | ISCAS | Speed-up of RISC Processor Computation using ADAPTO. | Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re |
| 2009 | ISCAS | Improved Large-signal Model for Vacuum Triodes. | Gian Carlo Cardarilli, Marco Re, Leonardo Di Carlo |
| 2008 | ACSSC | Reducing power dissipation in pipelined accumulators. | Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re |
| 2008 | IOLTS | Totally Fault Tolerant RNS Based FIR Filters. | Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano |
| 2008 | ISCAS | ADAPTO: full-adder based reconfigurable architecture for bit level operations. | Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli |
| 2007 | IOLTS | Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. | Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante |
| 2007 | ISCAS | Low-power adaptive filter based on RNS components. | G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2006 | IOLTS | Localization of Faults in Radix-n Signed Digit Adders. | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
| 2006 | ISCAS | Concurrent error detection in Reed Solomon decoders. | Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
| 2006 | ISCAS | Fault tolerant design of signed digit based FIR filters. | Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
| 2006 | ISCAS | Optimized QPSK modulator for DVB-S applications. | Gian Carlo Cardarilli, Andrea Del Re, Marco Re, Lorenzo Simone |
| 2005 | IOLTS | Design of a Self Checking Reed Solomon Encoder. | Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
| 2005 | ISCAS | Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. | Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2004 | IOLTS | A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
| 2004 | ISCAS | Low-power implementation of polyphase filters in Quadratic Residue Number system. | Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2003 | ISCAS | A fault tolerant hardware based file system manager for solid state mass memory. | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
| 2003 | ISCAS | IP based reconfigurable digital platform for satellite communications. | Gian Carlo Cardarilli, Andrea Del Re, Marco Re |
| 2003 | ISCAS | Power-delay tradeoffs in residue number system. | Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re |
| 2002 | IOLTS | Bit Flip Injection in Processor-Based Architectures: A Case Study. | Gian Carlo Cardarilli, F. Kaddour, A. Leandri, Marco Ottavi, Salvatore Pontarelli, Raoul Velazco |
| 2002 | ISCAS | Power characterization of digital filters implemented on FPGA. | Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re |
| 2002 | ISCAS | A self-checking cell logic block for fault tolerant FPGAs. | Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano |
| 2001 | ISCAS | Tradeoffs between residue number system and traditional FIR filters. | Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli |
| 2001 | ISCAS | Development of a dynamic routing system for a fault tolerant solid state mass memory. | Marco Ottavi, Gian Carlo Cardarilli, Panfilo Marinucci, Salvatore Pontarelli, Adelio Salsano |
| 2001 | ISCAS | FPGA realization of RNS to binary signed conversion architecture. | Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono |
| 2000 | ISCAS | Development of an evaluation model for the design of fault-tolerant solid state mass memory. | Gian Carlo Cardarilli, Panfilo Marinucci, Adelio Salsano |
| 2000 | ISCAS | FPGA implementation of a demux based on a multirate filter bank. | Marco Re, Gian Carlo Cardarilli, Andrea Del Re, Roberto Lojacono |
| 2000 | ISCAS | A CAD environment for fuzzy systems HW/SW mapping. | Marco Re, Marcello Salmeri, Gian Carlo Cardarilli |
| 1999 | ISCAS | Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion. | Alberto L. Sangiovanni-Vincentelli, Marco Re, Luciano Lavagno, Gian Carlo Cardarilli, Roberto Lojacono |
| 1990 | ICASSP | RNS approach to full parallel linear combinators. | Mario Salerno, Gian Carlo Cardarilli, Roberto Lojacono, F. Sargeni |
| 1989 | ICASSP | RNS approach to fast dividers. | Gian Carlo Cardarilli, Roberto Lojacono, Mario Salerno |
| 1988 | ICASSP | RNS Fourier transforms. | Pietro Burrascano, Gian Carlo Cardarilli, Roberto Lojacono, Giuseppe Martinelli, Mario Salerno |